<?xml version='1.0'?>
<?xml-stylesheet href="optable.xsl" type="text/xsl"?>
<x86optable>

  <!--
      The most important elements of each instruction definition are the
      pfx (prefix), opc (opcode), and opr (operand) elements.  Each is a
      CDATA element consisting of blank-separated words.  Upper and lower
      case are equivalent.

      <pfx></pfx>

      pfx describes the set of valid prefixes that can precede the main
      opcode without turning it into a different instruction. These may
      be:

      aso   accepts address size override
      oso   accepts operand size override
      seg   accepts a segment override
      rexw, rexr, rexx, rexb
            uses the indicated REX bit
      vexl  accepts the vex.L prefix bit, in other words, the vexl
            bit can be used in the decoding of the avx instruction.

      <opr></opr>

      [T][s]

      Size Suffix
      ===========

      x     - If vex.L = 1 => m256/YMM
                 vex.L = 0 => m128/XMM

      opc words may be actual byte values (two hex digits), or may be one of
      the following:
      /sse=66,f3,f2 - required prefix (always first, and always
        followed by 0f)
      /3dnow=00-ff - this is a 3DNow opcode (only in a definition of the
        form 0f 0f 3dnow=<byte>)
      /a=16,32,64 - has this address size
      /m=16,32,64,!64 - applicable only when the CPU is in this mode
      /o=16,32,64 - has this operand size
      /mod=11,!11 - has ModR/M with 11 or not-11 in the Mod field
      /reg=0-7 - has ModR/M with this value in the reg field
      /rm=0-7 - has ModR/M with this value in the R/M field (only with
        /mod=11)
      /x87=00-3f - X87 opcode with this value in the low 6 bits of the
        following "ModR/M" byte (only with /mod=11 and no other modifiers)

      opr words follow the Intel documentation somewhat, and specify the
      location and the size of the operand.  The OperandDict table in
      ud_itab.py maps these words to named OP_ and SZ_ constants for the
      location and size respectively.  These constants are defined in
      decode.h, q.v. for details.

      The mode element affects instruction semantics but not decoding:
          inv64 - invalid in 64-bit mode
      def64 - default operand size is 64 bits in 64-bit mode

      cpuid

        The cpuid element maybe applied to an instruction or a specific
        definition of the instruction. One ore more strings define the
        cpuid features that the instruction (or a definition belongs to)

        Values are: sse, sse2, sse3, sse4, sse4.1, sse4.2, avx

      AVX Instructions

      AVX instructions can be described in two ways. One, the explicit
      form, and the other that promotes an existing sse instruction
      definition to its avx form.

      If an instruction is defined to be in cpuid=avx, but is defined in
      the legacy form (using /sse= extensions), then the opcode generator
      will infer that as two definitions, one the see instruction and the
      other, an inferred avx instruction.

      In generating the sse definition from the above, the following
      transformations happen,

        - /vexw and /vexl extensions (if any) are removed
        - The operands H and L are removed. Operands specified on
          the right to removed operands are shifted to the left
          position.
        - The vexl prefix is removed.
        - "avx" is removed form the cpuid definition.

     In generating the avx definition from the above, the following
     transformations happen,

        - c4 is inserted in the 0th position of the opcode string
        - /sse extension is removed
        - A new /vex extension is constructed using /sse, 0f, 38 and
          3a opcodes (if any).
        - Operands V, W, H, and U are marked explicitly to have the
          size suffix "x"

     If the above transformations do not generate the required
     definitions, the instructions will need to be defined separately.
    
    EFLAGS
      The <eflags> field describe the status of the EFLAGS register
    once the instruction has been executed. This is an array of eleven
    values, for each bit of the EFLAGS register.
    
      The order of the flags is OF, SF, ZF, AF, PF, CF, TF, IF, DF, NT, RF, AC.
      Each flag can have one of these values:
          _ : the flag is not used
          T : flag is tested
          M : flag is modified according to the result of the operation
          R : flag is reset (its value is 0)
          S : flag is set (its value is 1)
          U : flag is undefined
          P : flag is set to its prior value (like push / pop)

      By default, we assume that the mask value is "____________".

      Note that if a flag is marked as modified, it may also be tested at the same time.

  -->
	
	<!-- 
		Note: We must avoid this instruction colliding with the XOP instructions
		as it has the same first byte 0x8F. The next byte should have the low 4 bits
		>= 8 if it is XOP otherwise it is a normal POP instruction.
		
		We encode this instruction in the VEX table to work around this.
	-->

    <instruction>
        <mnemonic>pop</mnemonic>
		<cpuid>xop avx</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=10 /reg=0</opc>
            <opr>Ev</opr>
			<access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>aaa</mnemonic>
        <eflags source='scrape'>UUUMUM______</eflags>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <def>
            <opc>37 /m=!64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aad</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_def>ax</implicit_register_def>
        <eflags source='scrape'>UMMUMU______</eflags>
        <def>
            <opc>d5 /m=!64</opc>
            <opr>Ib</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aam</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_def>ax</implicit_register_def>
        <eflags source='scrape'>UMMUMU______</eflags>
        <def>
            <opc>d4 /m=!64</opc>
            <opr>Ib</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aas</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <eflags source='scrape'>UUUMUM______</eflags>
        <def>
            <opc>3f /m=!64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>adc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>10</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>11</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>12</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>13</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>14</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>15</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=2</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=2 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=2</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=2</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>add</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>00</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>01</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>02</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>03</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>04</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>05</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=0</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=0 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=0</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=0</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 58</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 58</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 58</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 58</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addsubpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>/sse=66 0f d0</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>addsubps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>/sse=f2 0f d0</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aesdec</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 de</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aesdeclast</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 df</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aesenc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <cpuid>aesni</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 dc</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aesenclast</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <cpuid>aesni avx</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 dd</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
			<cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aesimc</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 db</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>aeskeygenassist</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a df</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>and</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>RMMUMR______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>20</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>21</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>22</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>23</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>24</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>25</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>80 /reg=4</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=4 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=4</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=4</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>andpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 54</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>andps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>0f 54</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>andnpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>/sse=66 0f 55</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>andnps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>0f 55</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>arpl</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso</pfx>
            <opc>63 /m=!64</opc>
            <opr>Ew Gw</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsxd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexx rexr rexb</pfx>
            <opc>63 /m=64</opc>
            <opr>Gq Ed</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>call</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=2 /m=!64</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=2 /m=64</opc>
            <opr>Eq</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=3</opc>
            <opr>Fv</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>e8</opc>
            <opr>Jz</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>9a /m=!64</opc>
            <opr>Av</opr>
			<access source='manual'>N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cbw</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_def>ax</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>98 /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cwde</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>98 /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cdqe</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>98 /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>clac</mnemonic>
        <eflags source='manual'>___________R</eflags>
        <def>
            <opc>0f 01 /reg=1 /mod=11 /rm=2</opc>
            <cpuid>smap</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>clc</mnemonic>
        <eflags source='scrape'>_____R______</eflags>
        <def>
            <opc>f8</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cld</mnemonic>
        <eflags source='scrape'>________R___</eflags>
        <def>
            <opc>fc</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>clflush</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /reg=7 /mod=!11</opc>
            <opr>Mb</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>clgi</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=5</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cli</mnemonic>
        <eflags source='scrape'>_______R____</eflags>
        <def>
            <opc>fa</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>clts</mnemonic>
        <implicit_register_use>cr0</implicit_register_use>
        <implicit_register_def>cr0</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 06</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmc</mnemonic>
        <eflags source='scrape'>_____M______</eflags>
        <def>
            <opc>f5</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovo</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>T___________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 40</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovno</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>T___________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 41</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>_____T______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 42</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovae</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>_____T______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 43</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmove</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 44</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovne</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 45</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovbe</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T__T______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 46</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmova</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T__T______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 47</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovs</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>_T__________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 48</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovns</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>_T__________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 49</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovp</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____T_______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4a</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovnp</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____T_______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4b</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovl</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>TT__________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4c</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovge</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>TT__________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4d</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovle</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>TTT_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4e</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmovg</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>TTT_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 4f</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmp</mnemonic>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>38</opc>
            <opr>Eb Gb</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>39</opc>
            <opr>Ev Gv</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>3a</opc>
            <opr>Gb Eb</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>3b</opc>
            <opr>Gv Ev</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <opc>3c</opc>
            <opr>AL Ib</opr>
			<access source='manual'>R N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>3d</opc>
            <opr>rAX sIz</opr>
			<access source='manual'>R N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=7</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>R N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=7 /m=!64</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>R N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=7</opc>
            <opr>Ev sIz</opr>
			<access source='manual'>R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=7</opc>
            <opr>Ev sIb</opr>
			<access source='manual'>R N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmppd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f c2</opc>
            <opr>V H W Ib</opr>
			<access source='manual'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>
	
	<!-- pseudo ops for cmppd -->
	<instruction><mnemonic>cmpeqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpltpd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmplepd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpunordpd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpneqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnltpd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnlepd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpordpd</mnemonic><def/></instruction>
	
	<instruction><mnemonic>vcmpeqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpltpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunordpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnltpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpordpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_uqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngtpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalsepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_oqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgtpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptruepd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_ospd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplt_oqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmple_oqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunord_spd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_uspd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlt_uqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnle_uqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpord_spd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_uspd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnge_uqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngt_uqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalse_ospd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_ospd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpge_oqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgt_oqpd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptrue_uspd</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>cmpps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f c2</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

	<instruction><mnemonic>cmpeqps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpltps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpleps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpunordps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpneqps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnltps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnleps</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpordps</mnemonic><def/></instruction>
	
	<instruction><mnemonic>vcmpeqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpltps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpleps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunordps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnltps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnleps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpordps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_uqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngeps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngtps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalseps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_oqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgeps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgtps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptrueps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_osps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplt_oqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmple_oqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunord_sps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_usps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlt_uqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnle_uqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpord_sps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_usps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnge_uqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngt_uqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalse_osps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_osps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpge_oqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgt_oqps</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptrue_usps</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>cmpsb</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz seg</pfx>
            <opc>a6</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmpsw</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz oso rexw seg</pfx>
            <opc>a7 /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmpsd</mnemonic>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <implicit_register_use>rsi</implicit_register_use>
            <implicit_register_use>rdi</implicit_register_use>
            <implicit_register_def>rsi</implicit_register_def>
            <implicit_register_def>rdi</implicit_register_def>
            <pfx>repz oso rexw seg</pfx>
            <opc>a7 /o=32</opc>
        </def>
        <def>
            <first_operand_access>RW</first_operand_access>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f c2</opc>
            <opr>V H MqU Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

	<instruction><mnemonic>cmpeqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpltsd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmplesd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpunordsd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpneqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnltsd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnlesd</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpordsd</mnemonic><def/></instruction>
	
	<instruction><mnemonic>vcmpeqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpltsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunordsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnltsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpordsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_uqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngtsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalsesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_oqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgtsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptruesd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_ossd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplt_oqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmple_oqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunord_ssd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_ussd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlt_uqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnle_uqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpord_ssd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_ussd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnge_uqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngt_uqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalse_ossd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_ossd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpge_oqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgt_oqsd</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptrue_ussd</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>cmpsq</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz oso rexw seg</pfx>
            <opc>a7 /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmpss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f c2</opc>
            <opr>V H MdU Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

	<instruction><mnemonic>cmpeqss</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpltss</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpless</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpunordss</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpneqss</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnltss</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpnless</mnemonic><def/></instruction>
	<instruction><mnemonic>cmpordss</mnemonic><def/></instruction>
	
	<instruction><mnemonic>vcmpeqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpltss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpless</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunordss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnltss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnless</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpordss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_uqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngess</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngtss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalsess</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_oqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgess</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgtss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptruess</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_osss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmplt_oqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmple_oqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpunord_sss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_usss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnlt_uqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnle_uqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpord_sss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpeq_usss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpnge_uqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpngt_uqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpfalse_osss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpneq_osss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpge_oqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmpgt_oqss</mnemonic><def/></instruction>
	<instruction><mnemonic>vcmptrue_usss</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>cmpxchg</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f b0</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b1</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmpxchg8b</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_use>rdx</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <implicit_register_def>rdx</implicit_register_def>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f c7 /mod=!11 /reg=1 /o=16</opc>
            <opr>Mq</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f c7 /mod=!11 /reg=1 /o=32</opc>
            <opr>Mq</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cmpxchg16b</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_use>rdx</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <implicit_register_def>rdx</implicit_register_def>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f c7 /mod=!11 /reg=1 /o=64</opc>
            <opr>Mdq</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>comisd</mnemonic>
        <eflags source='scrape'>RRMRMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 2f</opc>
            <opr>Vsd Wsd</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>comiss</mnemonic>
        <eflags source='scrape'>RRMRMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 2f</opc>
            <opr>V MdU</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cpuid</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>ebx</implicit_register_def>
        <implicit_register_def>ecx</implicit_register_def>
        <implicit_register_def>edx</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f a2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtdq2pd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f e6</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse2</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vcvtdq2pd</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=f3_0f /vexl=0 e6</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=f3_0f /vexl=1 e6</opc>
            <opr>V MdqU</opr> <!-- we need to coerce the reg in MdqU to be amm not ymm -->
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>cvtdq2ps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 5b</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtpd2dq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f2 0f e6</opc>
            <opr>Vdq W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtpd2pi</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 2d</opc>
            <opr>P W</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtpd2ps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5a</opc>
            <opr>Vdq W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtpi2ps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 2a</opc>
            <opr>V Q</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtpi2pd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 2a</opc>
            <opr>V Q</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtps2dq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5b</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtps2pd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 5a</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse2</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vcvtps2pd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=0f 5a /vexl=0</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=0f 5a /vexl=1</opc>
            <opr>V MdqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>cvtps2pi</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 2d</opc>
            <opr>P MqU</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtsd2si</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 2d</opc>
            <opr>Gy MqU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtsd2ss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 5a</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtsi2sd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 2a</opc>
            <opr>V H Ey</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtsi2ss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 2a</opc>
            <opr>V H Ey</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtss2sd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 5a</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvtss2si</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 2d</opc>
            <opr>Gy MdU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttpd2dq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e6</opc>
            <opr>Vdq W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttpd2pi</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 2c</opc>
            <opr>P W</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttps2dq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 5b</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttps2pi</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 2c</opc>
            <opr>P MqU</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttsd2si</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 2c</opc>
            <opr>Gy MqU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cvttss2si</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 2c</opc>
            <opr>Gy MdU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cwd</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_def>ax</implicit_register_def>
        <implicit_register_def>dx</implicit_register_def>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>99 /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cdq</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>edx</implicit_register_def>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>99 /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>cqo</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <implicit_register_def>rdx</implicit_register_def>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>99 /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>daa</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <eflags source='scrape'>UMMMMM______</eflags>
        <def>
            <opc>27 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>das</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <eflags source='scrape'>UMMMMM______</eflags>
        <def>
            <opc>2f /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>dec</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMM_______</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>48</opc>
            <opr>R0z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>49</opc>
            <opr>R1z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4a</opc>
            <opr>R2z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4b</opc>
            <opr>R3z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4c</opc>
            <opr>R4z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4d</opc>
            <opr>R5z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4e</opc>
            <opr>R6z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>4f</opc>
            <opr>R7z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>fe /reg=1</opc>
            <opr>Eb</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=1</opc>
            <opr>Ev</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>div</mnemonic>
        <first_operand_access>R</first_operand_access>
        <eflags source='scrape'>UUUUUU______</eflags>
        <def>
            <implicit_register_use>ax</implicit_register_use>
            <implicit_register_use>dx</implicit_register_use>
            <implicit_register_def>ax</implicit_register_def>
            <implicit_register_def>dx</implicit_register_def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=6</opc>
            <opr>Ev</opr>
            <access source='manual'>R</access>
        </def>
        <def>
            <implicit_register_use>ax</implicit_register_use>
            <implicit_register_def>ax</implicit_register_def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=6</opc>
            <opr>Eb</opr>
            <access source='manual'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>divpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5e</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>divps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso vexl rexr rexx rexb</pfx>
            <opc>0f 5e</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>divsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 5e</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>divss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 5e</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>dppd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 41</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>dpps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 40</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>emms</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <opc>0f 77</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>enter</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>c8</opc>
            <opr>Iw Ib</opr>
            <access source='scrape'>N N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>extractps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 17</opc>
            <opr>MdRy V Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>f2xm1</mnemonic>
        <implicit_register_use>st0</implicit_register_use>
        <implicit_register_def>st0</implicit_register_def>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=30</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fabs</mnemonic>
        <implicit_register_use>st0</implicit_register_use>
        <implicit_register_def>st0</implicit_register_def>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=21</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fadd</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=0</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=0</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=00</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=01</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=02</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=03</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=04</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=05</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=06</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=07</opc>
            <opr>ST7 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=00</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=01</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=02</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=03</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=04</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=05</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=06</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=07</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>faddp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=00</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=01</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=02</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=03</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=04</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=05</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=06</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=07</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fbld</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=4</opc>
            <opr>Mt</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fbstp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=6</opc>
            <opr>Mt</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fchs</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=20</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnclex</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=22</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovb</mnemonic>
        <eflags source='scrape'>_____T______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>da /mod=11 /x87=00</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=01</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=02</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=03</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=04</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=05</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=06</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=07</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmove</mnemonic>
        <eflags source='scrape'>__T_________</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>da /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=09</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=0f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovbe</mnemonic>
        <eflags source='scrape'>__T__T______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>da /mod=11 /x87=10</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=11</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=12</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=13</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=14</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=15</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=16</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=17</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovu</mnemonic>
        <eflags source='scrape'>____T_______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>da /mod=11 /x87=18</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=19</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>da /mod=11 /x87=1f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovnb</mnemonic>
        <eflags source='scrape'>_____T______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=00</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=01</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=02</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=03</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=04</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=05</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=06</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=07</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovne</mnemonic>
        <eflags source='scrape'>__T_________</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=09</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=0f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovnbe</mnemonic>
        <eflags source='scrape'>__T__T______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=10</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=11</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=12</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=13</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=14</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=15</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=16</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=17</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcmovnu</mnemonic>
        <eflags source='scrape'>____T_______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=18</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=19</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=1f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fucomi</mnemonic>
        <eflags source='scrape'>__M_MM______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=28</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=29</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=2f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcom</mnemonic>
        <eflags source="manual">___________</eflags>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=2</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=2</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=10</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=11</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=12</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=13</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=14</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=15</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=16</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=17</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcom2</mnemonic>
        <eflags source='manual'>____________</eflags>
        <cpuid>X87 UNDOC</cpuid>
        <def>
            <opc>dc /mod=11 /x87=10</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=11</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=12</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=13</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=14</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=15</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=16</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=17</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcomp3</mnemonic>
        <eflags source='manual'>____________</eflags>
        <cpuid>X87 UNDOC</cpuid>
        <def>
            <opc>dc /mod=11 /x87=18</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=19</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=1f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcomi</mnemonic>
        <eflags source='manual'>RRMRMM______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=30</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=31</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=32</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=33</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=34</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=35</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=36</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>db /mod=11 /x87=37</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fucomip</mnemonic>
        <eflags source="manual">RRMRMM______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>df /mod=11 /x87=28</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=29</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=2f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcomip</mnemonic>
        <eflags source="manual">RRMRMM______</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>df /mod=11 /x87=30</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=31</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=32</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=33</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=34</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=35</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=36</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=37</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcomp</mnemonic>
        <eflags source='manual'>____________</eflags>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=3</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=3</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=18</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=19</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=1f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcomp5</mnemonic>
        <eflags source='manual'>____________</eflags>
        <cpuid>X87 UNDOC</cpuid>
        <def>
            <opc>de /mod=11 /x87=10</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=11</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=12</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=13</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=14</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=15</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=16</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=17</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcompp</mnemonic>
        <eflags source='manual'>____________</eflags>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=19</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fcos</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3f</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fdecstp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=36</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fdiv</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=6</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=38</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=39</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=3f</opc>
            <opr>ST7 ST0</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=6</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=30</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=31</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=32</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=33</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=34</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=35</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=36</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=37</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fdivp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=38</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=39</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=3f</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fdivr</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=7</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=30</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=31</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=32</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=33</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=34</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=35</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=36</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=37</opc>
            <opr>ST7 ST0</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=7</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=38</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=39</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=3f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fdivrp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=30</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=31</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=32</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=33</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=34</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=35</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=36</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=37</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>femms</mnemonic>
        <def>
            <opc>0f 0e</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ffree</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>dd /mod=11 /x87=00</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=01</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=02</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=03</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=04</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=05</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=06</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=07</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ffreep</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>df /mod=11 /x87=00</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=01</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=02</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=03</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=04</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=05</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=06</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=07</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ficom</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=2</opc>
            <opr>Mw</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=2</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ficomp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=3</opc>
            <opr>Mw</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=3</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fild</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=0</opc>
            <opr>Mw</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=5</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=0</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fincstp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=37</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fninit</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=23</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fiadd</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=0</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=0</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fidivr</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=7</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=7</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fidiv</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=6</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=6</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fisub</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=4</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=4</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fisubr</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=5</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=5</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fist</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=2</opc>
            <opr>Mw</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=2</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fistp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=3</opc>
            <opr>Mw</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=7</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=3</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fisttp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=1</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=1</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>df /mod=!11 /reg=1</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fld</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=5</opc>
            <opr>Mt</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=0</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=0</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=00</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=01</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=02</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=03</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=04</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=05</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=06</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=07</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fld1</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=28</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldl2t</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=29</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldl2e</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=2a</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldpi</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=2b</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldlg2</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=2c</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldln2</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=2d</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldz</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=2e</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldcw</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=5</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fldenv</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=4</opc>
            <opr>M</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fmul</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=1</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=09</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=0f</opc>
            <opr>ST7 ST0</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=1</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=09</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=0f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fmulp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=09</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=0f</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fimul</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>da /mod=!11 /reg=1</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>de /mod=!11 /reg=1</opc>
            <opr>Mw</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnop</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=10</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fndisi</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=21</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fneni</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=20</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnsetpm</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=24</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fpatan</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=33</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fprem</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=38</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fprem1</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=35</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fptan</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>frndint</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3c</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>frstor</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=4</opc>
            <opr>M</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>frstpm</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>db /mod=11 /x87=25</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnsave</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=6</opc>
            <opr>M</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fscale</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3d</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsin</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3e</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsincos</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3b</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsqrt</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=3a</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fstp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>db /mod=!11 /reg=7</opc>
            <opr>Mt</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=3</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=3</opc>
            <opr>Md</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=18</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=19</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=1f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fstp1</mnemonic>
        <def>
            <opc>d9 /mod=11 /x87=18</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=19</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=1f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fstp8</mnemonic>
        <def>
            <opc>df /mod=11 /x87=10</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=11</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=12</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=13</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=14</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=15</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=16</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=17</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fstp9</mnemonic>
        <def>
            <opc>df /mod=11 /x87=18</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=19</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=1f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fst</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=2</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=2</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=10</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=11</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=12</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=13</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=14</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=15</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=16</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=17</opc>
            <opr>ST7</opr>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>fnstcw</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=7</opc>
            <opr>Mw</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnstenv</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d9 /mod=!11 /reg=6</opc>
            <opr>M</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fnstsw</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dd /mod=!11 /reg=7</opc>
            <opr>Mw</opr>
			<access source='manual'>W</access>
        </def>
        <def>
            <opc>df /mod=11 /x87=20</opc>
            <opr>AX</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <!-- Collides with wait -->
    <!--<instruction>
        <mnemonic>fstsw</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>9b dd /mod=!11 /reg=7</opc>
            <opr>Mw</opr>
			<access source='manual'>W</access>
        </def>
        <def>
            <opc>9b df /mod=11 /x87=20</opc>
            <opr>AX</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>-->

    <instruction>
        <mnemonic>fsub</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=4</opc>
            <opr>Md</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=4</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=20</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=21</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=22</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=23</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=24</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=25</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=26</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=27</opc>
            <opr>ST0 ST7</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=28</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=29</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=2f</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsubp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=28</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=29</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2a</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2b</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2c</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2d</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2e</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=2f</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsubr</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>dc /mod=!11 /reg=5</opc>
            <opr>Mq</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=28</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=29</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d8 /mod=11 /x87=2f</opc>
            <opr>ST0 ST7</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=20</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=21</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=22</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=23</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=24</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=25</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=26</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>dc /mod=11 /x87=27</opc>
            <opr>ST7 ST0</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d8 /mod=!11 /reg=5</opc>
            <opr>Md</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fsubrp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>de /mod=11 /x87=20</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=21</opc>
            <opr>ST1 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=22</opc>
            <opr>ST2 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=23</opc>
            <opr>ST3 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=24</opc>
            <opr>ST4 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=25</opc>
            <opr>ST5 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=26</opc>
            <opr>ST6 ST0</opr>
        </def>
        <def>
            <opc>de /mod=11 /x87=27</opc>
            <opr>ST7 ST0</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ftst</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=24</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fucom</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>dd /mod=11 /x87=20</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=21</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=22</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=23</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=24</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=25</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=26</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=27</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fucomp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>dd /mod=11 /x87=28</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=29</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=2f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fucompp</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>da /mod=11 /x87=29</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fxam</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=25</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fxch</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=08</opc>
            <opr>ST0 ST0</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=09</opc>
            <opr>ST0 ST1</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0a</opc>
            <opr>ST0 ST2</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0b</opc>
            <opr>ST0 ST3</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0c</opc>
            <opr>ST0 ST4</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0d</opc>
            <opr>ST0 ST5</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0e</opc>
            <opr>ST0 ST6</opr>
        </def>
        <def>
            <opc>d9 /mod=11 /x87=0f</opc>
            <opr>ST0 ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fxch4</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>dd /mod=11 /x87=08</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=09</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>dd /mod=11 /x87=0f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fxch7</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>df /mod=11 /x87=08</opc>
            <opr>ST0</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=09</opc>
            <opr>ST1</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0a</opc>
            <opr>ST2</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0b</opc>
            <opr>ST3</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0c</opc>
            <opr>ST4</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0d</opc>
            <opr>ST5</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0e</opc>
            <opr>ST6</opr>
        </def>
        <def>
            <opc>df /mod=11 /x87=0f</opc>
            <opr>ST7</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fxrstor</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /mod=!11 /reg=1</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>
	
    <instruction><mnemonic>fxrstor64</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>fxsave</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /mod=!11 /reg=0</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>
	
    <instruction><mnemonic>fxsave64</mnemonic><def/></instruction>
	
    <instruction>
        <mnemonic>fxtract</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=34</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fyl2x</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=31</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>fyl2xp1</mnemonic>
        <cpuid>X87</cpuid>
        <def>
            <opc>d9 /mod=11 /x87=39</opc>
        </def>
    </instruction>

     <instruction>
        <mnemonic>hlt</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>f4</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>idiv</mnemonic>
        <eflags source='scrape'>UUUUUU______</eflags>
        <def>
            <implicit_register_use>rax</implicit_register_use>
            <implicit_register_use>rdx</implicit_register_use>
            <implicit_register_def>rax</implicit_register_def>
            <implicit_register_def>rdx</implicit_register_def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=7</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <implicit_register_use>rax</implicit_register_use>
            <implicit_register_def>rax</implicit_register_def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=7</opc>
            <opr>Eb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>in</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>e4</opc>
            <opr>AL Ib</opr>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>e5</opc>
            <opr>eAX Ib</opr>
        </def>
        <def>
            <opc>ec</opc>
            <opr>AL DX</opr>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>ed</opc>
            <opr>eAX DX</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>imul</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MUUUUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f af</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <implicit_register_use>al</implicit_register_use>
            <implicit_register_def>ax</implicit_register_def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=5</opc>
            <opr>Eb</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <implicit_register_use>rax</implicit_register_use>
            <implicit_register_def>rax</implicit_register_def>
            <implicit_register_def>rdx</implicit_register_def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=5</opc>
            <opr>Ev</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>69</opc>
            <opr>Gv Ev Iz</opr>
            <access source='scrape'>RW R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>6b</opc>
            <opr>Gv Ev sIb</opr>
            <access source='scrape'>RW R N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>inc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMM_______</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>40</opc>
            <opr>R0z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>41</opc>
            <opr>R1z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>42</opc>
            <opr>R2z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>43</opc>
            <opr>R3z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>44</opc>
            <opr>R4z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>45</opc>
            <opr>R5z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>46</opc>
            <opr>R6z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>47</opc>
            <opr>R7z</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=0</opc>
            <opr>Ev</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>fe /reg=0</opc>
            <opr>Eb</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>insb</mnemonic>
        <implicit_register_use>dx</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg</pfx>
            <opc>6c</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>insw</mnemonic>
        <implicit_register_use>dx</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep oso seg</pfx>
            <opc>6d /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>insd</mnemonic>
        <implicit_register_use>dx</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep oso seg</pfx>
            <opc>6d /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>int1</mnemonic>
        <eflags source='scrape'>______R__R__</eflags>
        <def>
            <opc>f1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>int3</mnemonic>
        <eflags source='scrape'>______R__R__</eflags>
        <def>
            <opc>cc</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>int</mnemonic>
        <eflags source='scrape'>______R__R__</eflags>
        <def>
            <opc>cd</opc>
            <opr>Ib</opr>
            <access source='scrape'>N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>into</mnemonic>
        <eflags source='scrape'>T_____R__R__</eflags>
        <def>
            <opc>ce /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invd</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 08</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invept</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
			<opc>/sse=66 0f 38 80 /m=32</opc>
            <opr>Gd Mo</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 80 /m=64</opc>
            <opr>Gq Mo</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invlpg</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=7 /mod=!11</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invlpga</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=7</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invvpid</mnemonic>
        <vendor>intel</vendor>
        <def>
            <opc>/sse=66 0f 38 81 /m=32</opc>
            <opr>Gd Mo</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <opc>/sse=66 0f 38 81 /m=64</opc>
            <opr>Gq Mo</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>iretw</mnemonic>
        <eflags source='scrape'>PPPPPPPPPT__</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>cf /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>iretd</mnemonic>
        <eflags source='scrape'>PPPPPPPPPT__</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>cf /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>iretq</mnemonic>
        <eflags source='scrape'>PPPPPPPPPT__</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>cf /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jo</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>T___________</eflags>
        <def>
            <opc>70</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 80</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jno</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>T___________</eflags>
        <def>
            <opc>71</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 81</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jb</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>_____T______</eflags>
        <def>
            <opc>72</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 82</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jae</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>_____T______</eflags>
        <def>
            <opc>73</opc>
            <opr>Jb</opr>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 83</opc>
            <opr>Jz</opr>
            <mode>def64</mode>
        </def>
    </instruction>

	<!-- we default to JZ/JNZ but keep the JE/JNE mnemonic available -->
	
	<instruction><mnemonic>je</mnemonic><def/></instruction>
	<instruction><mnemonic>jne</mnemonic><def/></instruction>
		
    <instruction>
        <mnemonic>jz</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <opc>74</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 84</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jnz</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <opc>75</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 85</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jbe</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>__T__T______</eflags>
        <def>
            <opc>76</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 86</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ja</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>__T__T______</eflags>
        <def>
            <opc>77</opc>
            <opr>Jb</opr>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 87</opc>
            <opr>Jz</opr>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>js</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>_T__________</eflags>
        <def>
            <opc>78</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 88</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jns</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>_T__________</eflags>
        <def>
            <opc>79</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 89</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jp</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____T_______</eflags>
        <def>
            <opc>7a</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8a</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jnp</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____T_______</eflags>
        <def>
            <opc>7b</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8b</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jl</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>TT__________</eflags>
        <def>
            <opc>7c</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8c</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jge</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>TT__________</eflags>
        <def>
            <opc>7d</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8d</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jle</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>TTT_________</eflags>
        <def>
            <opc>7e</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8e</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jg</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>TTT_________</eflags>
        <def>
            <opc>7f</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>0f 8f</opc>
            <opr>Jz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jcxz</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso</pfx>
            <opc>e3 /a=16</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jecxz</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso</pfx>
            <opc>e3 /a=32</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jrcxz</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso</pfx>
            <opc>e3 /a=64</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>jmp</mnemonic>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=4</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=5</opc>
            <opr>Fv</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>e9</opc>
            <opr>Jz</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>ea /m=!64</opc>
            <opr>Av</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <opc>eb</opc>
            <opr>Jb</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lahf</mnemonic>
        <implicit_register_def>ah</implicit_register_def>
        <eflags source='manual'>_TTTTT______</eflags>
        <def>
            <opc>9f</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lar</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 02</opc>
            <opr>Gv Ew</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ldmxcsr</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /reg=2 /mod=!11</opc>
            <opr>Md</opr>
			<access source='manual'>R</access>
			<cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lds</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso</pfx>
            <opc>c5 /vex=none /m=!64</opc>
            <opr>Gv M</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lea</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>8d</opc>
            <opr>Gv M</opr>
			<access source='manual'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>les</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>es</implicit_register_use>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso</pfx>
            <opc>c4 /m=!64</opc>
            <opr>Gv M</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lfs</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>fs</implicit_register_use>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b4</opc>
            <opr>Gz M</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lgs</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>fs</implicit_register_use>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b5</opc>
            <opr>Gz M</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lidt</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=3 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>ss</implicit_register_use>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b2</opc>
            <opr>Gv M</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>leave</mnemonic>
        <implicit_register_use>rbp</implicit_register_use>
        <implicit_register_def>rbp</implicit_register_def>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>c9</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>lfence</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <opc>0f ae /mod=11 /reg=5</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lgdt</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=2 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lldt</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 00 /reg=2</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lmsw</mnemonic>
        <implicit_register_def>cr0</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=6 /mod=!11</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=6 /mod=11</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lock</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>f0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lodsb</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg</pfx>
            <opc>ac</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lodsw</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>ax</implicit_register_def>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ad /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lodsd</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ad /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lodsq</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rax</implicit_register_def>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ad /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>loopne</mnemonic>
        <eflags source='scrape'>__T_________</eflags>
        <def>
            <opc>e0</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>loope</mnemonic>
        <eflags source='scrape'>__T_________</eflags>
        <def>
            <opc>e1</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>loop</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>e2</opc>
            <opr>Jb</opr>
            <access source='scrape'>N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lsl</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f 03</opc>
            <opr>Gv Ew</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ltr</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 00 /reg=3</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>maskmovq</mnemonic>
        <implicit_register_use>rdi</implicit_register_use>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f7 /mod=11</opc>
            <opr>P N</opr>
            <access source='scrape'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>maxpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5f</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>maxps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 5f</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>maxsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 5f</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>maxss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 5f</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mfence</mnemonic>
        <def>
            <opc>0f ae /mod=11 /reg=6</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>minpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>minps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 5d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>minsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 5d</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>minss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 5d</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>monitor</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_use>rdx</implicit_register_use>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 01 /reg=1 /mod=11 /rm=0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>montmul</mnemonic>
        <def>
            <opc>0f a6 /mod=11 /rm=0 /reg=0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mov</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags>___________</eflags>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c6 /mod=11 /reg=0</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c6 /mod=!11 /reg=0</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c7 /mod=11 /reg=0</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c7 /mod=!11 /reg=0</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>88</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>89</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>8a</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>8b</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>8c</opc>
            <opr>MwRv S</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>8e</opc>
            <opr>S MwRv</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <opc>a0</opc>
            <opr>AL Ob</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw</pfx>
            <opc>a1</opc>
            <opr>rAX Ov</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <opc>a2</opc>
            <opr>Ob AL</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw</pfx>
            <opc>a3</opc>
            <opr>Ov rAX</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b0</opc>
            <opr>R0b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b1</opc>
            <opr>R1b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b2</opc>
            <opr>R2b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b3</opc>
            <opr>R3b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b4</opc>
            <opr>R4b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b5</opc>
            <opr>R5b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b6</opc>
            <opr>R6b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>b7</opc>
            <opr>R7b Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>b8</opc>
            <opr>R0v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>b9</opc>
            <opr>R1v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>ba</opc>
            <opr>R2v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>bb</opc>
            <opr>R3v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>bc</opc>
            <opr>R4v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>bd</opc>
            <opr>R5v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>be</opc>
            <opr>R6v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>bf</opc>
            <opr>R7v Iv</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
			<eflags source='manual'>UUUUUU______</eflags>
            <pfx>rexr rexw rexb</pfx>
            <opc>0f 20</opc>
            <opr>R C</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
			<eflags source='manual'>UUUUUU______</eflags>
            <pfx>rexr rexw rexb</pfx>
            <opc>0f 21</opc>
            <opr>R D</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
			<eflags source='manual'>UUUUUU______</eflags>
            <pfx>rexr rexw rexb</pfx>
            <opc>0f 22</opc>
            <opr>C R</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
			<eflags source='manual'>UUUUUU______</eflags>
            <pfx>rexr rexw rexb</pfx>
            <opc>0f 23</opc>
            <opr>D R</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movapd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 28</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 29</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movaps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 28</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 29</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 6e /o=16</opc>
            <opr>P Ey</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 6e /o=32</opc>
            <opr>P Ey</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>

        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 6e /o=16</opc>
            <opr>V Ey</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 6e /o=32</opc>
            <opr>V Ey</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 7e /o=16</opc>
            <opr>Ey P</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 7e /o=32</opc>
            <opr>Ey P</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 7e /o=16</opc>
            <opr>Ey V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 7e /o=32</opc>
            <opr>Ey V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movhpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 16 /mod=!11</opc>
            <opr>V H Mq</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 17</opc>
            <opr>Mq V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movhps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 16 /mod=!11</opc>
            <opr>V H Mq</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 17</opc>
            <opr>Mq V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movlhps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 16 /mod=11</opc>
            <opr>V H U</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movlpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 12 /mod=!11</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 13</opc>
            <opr>Mq V</opr>
            <access source='scrape'>W R</access>
        </def>
        <cpuid>sse2 avx</cpuid>
    </instruction>

    <instruction>
        <mnemonic>movlps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 12 /mod=!11</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 13</opc>
            <opr>Mq V</opr>
            <access source='scrape'>W R</access>
        </def>
        <cpuid>sse avx</cpuid>
    </instruction>

    <instruction>
        <mnemonic>movhlps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 12 /mod=11</opc>
            <opr>V H U</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
		
    </instruction>

    <instruction>
        <mnemonic>movmskpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>oso rexr rexb vexl</pfx>
            <opc>/sse=66 0f 50</opc>
            <opr>Gd U</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movmskps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>oso rexr rexb vexl</pfx>
            <opc>0f 50</opc>
            <opr>Gd U</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntdq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e7</opc>
            <opr>Mx V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movnti</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f c3</opc>
            <opr>Mv Gy</opr>
			<access source='scrape'>W R</access>

        </def>
    </instruction>

    <instruction>
        <mnemonic>movntpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 2b</opc>
            <opr>M V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 2b</opc>
            <opr>M V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e7</opc>
            <opr>Mq P</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 6e /o=64</opc>
            <opr>P Eq</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 6e /o=64</opc>
            <opr>V Eq</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 7e /o=64</opc>
            <opr>Eq P</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 7e /o=64</opc>
            <opr>Eq V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 7e</opc>
            <opr>V MqU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f d6</opc>
            <opr>MqU V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 6f</opc>
            <opr>P Q</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 7f</opc>
            <opr>Q P</opr>
            <access source='scrape'>W R</access>
            <cpuid>mmx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg</pfx>
            <opc>a4</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>a5 /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <implicit_register_use>rsi</implicit_register_use>
            <implicit_register_def>rsi</implicit_register_def>
            <implicit_register_use>rdi</implicit_register_use>
            <implicit_register_def>rdi</implicit_register_def>
            <pfx>rep seg oso rexw</pfx>
            <opc>a5 /o=32</opc>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 10</opc>
            <opr>V MqU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 11</opc>
            <opr>MqU V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>a5 /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 10</opc>
            <opr>V MdU</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 11</opc>
            <opr>MdU V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsx</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f be</opc>
            <opr>Gv Eb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f bf</opc>
            <opr>Gy Ew</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movupd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 10</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 11</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movups</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 10</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 11</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movzx</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b6</opc>
            <opr>Gv Eb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b7</opc>
            <opr>Gy Ew</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mul</mnemonic>
        <eflags source='scrape'>MUUUUM______</eflags>
        <def>
            <implicit_register_use>al</implicit_register_use>
            <implicit_register_def>ax</implicit_register_def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=4</opc>
            <opr>Eb</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <implicit_register_use>rax</implicit_register_use>
            <implicit_register_def>rax</implicit_register_def>
            <implicit_register_def>rdx</implicit_register_def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=4</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mulpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 59</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mulps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 59</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mulsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 59</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mulss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 59</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mwait</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 01 /reg=1 /mod=11 /rm=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>neg</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=3</opc>
            <opr>Eb</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=3</opc>
            <opr>Ev</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>nop</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 19</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
        <!--<def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1a</opc>
            <opr>M</opr>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1b</opc>
            <opr>M</opr>
        </def>-->
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1c</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1d</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1e /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 1f</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>not</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=2</opc>
            <opr>Eb</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=2</opc>
            <opr>Ev</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>or</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>RMMUMR______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>08</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>09</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0a</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0b</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>0c</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>0d</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=1</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=1</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=1 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=1</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>orpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 56</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>orps</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 56</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>out</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>e6</opc>
            <opr>Ib AL</opr>
			<access source='manual'>N R</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>e7</opc>
            <opr>Ib eAX</opr>
			<access source='manual'>N R</access>
        </def>
        <def>
            <opc>ee</opc>
            <opr>DX AL</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>ef</opc>
            <opr>DX eAX</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>outsb</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep seg</pfx>
            <opc>6e</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>outsw</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep oso seg</pfx>
            <opc>6f /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>outsd</mnemonic>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <eflags source='scrape'>________T___</eflags>
        <def>
            <pfx>rep oso seg</pfx>
            <opc>6f /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>packsswb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 63</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 63</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>packssdw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 6b</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 6b</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>packuswb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 67</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 67</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f fc</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f fc</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f fd</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f fd</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f fe</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
            <cpuid>mmx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f fe</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>


    <instruction>
        <mnemonic>paddsb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f ec</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f ec</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f ed</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f ed</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddusb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f dc</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f dc</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddusw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f dd</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f dd</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pand</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f db</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f db</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pandn</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f df</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f df</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pavgb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e0</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e0</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pavgw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e3</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e3</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpeqb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 74</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 74</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpeqw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 75</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 75</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpeqd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 76</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 76</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpgtb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 64</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 64</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpgtw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 65</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 65</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpgtd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 66</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 66</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pextrb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexx rexr rexb</pfx>
            <opc>/sse=66 0f 3a 14 /vexw=0</opc>
            <opr>MbRd V Ib</opr>
            <access source='scrape'>W R N</access>
            <mode>def64</mode>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pextrd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexw rexb</pfx>
            <opc>/sse=66 0f 3a 16 /o=16 /vexw=0</opc>
            <opr>Ed V Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexw rexb</pfx>
            <opc>/sse=66 0f 3a 16 /o=32 /vexw=0</opc>
            <opr>Ed V Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pextrq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexb</pfx>
            <opc>/sse=66 0f 3a 16 /o=64 /vexw=1</opc>
            <opr>Eq V Ib</opr>
            <access source='scrape'>W R N</access>
            <mode>def64</mode>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

   <instruction>
        <mnemonic>pextrw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexb</pfx>
            <opc>/sse=66 0f c5</opc>
            <opr>Gd U Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse avx</cpuid>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f c5</opc>
            <opr>Gd N Ib</opr>
            <access source='scrape'>W R N</access>
        </def>
        <def>
            <pfx>aso rexw rexx rexr rexb</pfx>
            <opc>/sse=66 0f 3a 15</opc>
            <opr>MwRd V Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pinsrb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 20</opc>
            <opr>V MbRd Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pinsrw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f c4</opc>
            <opr>P MwRd Ib</opr>
            <access source='scrape'>W R N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f c4</opc>
            <opr>V H MwRd Ib</opr>
            <mode>def64</mode>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pinsrd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 22 /o=16</opc>
            <opr>V Ed Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1</cpuid>
        </def>

        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 22 /o=32</opc>
            <opr>V Ed Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pinsrq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 22 /o=64</opc>
            <opr>V Eq Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpinsrb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a 20 /vexw=0 /vexl=0</opc>
            <opr>V H MbRd Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpinsrd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a 22 /m=!64 /vexw=0 /vexl=0</opc>
            <opr>V H Ed Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a 22 /m=64 /vexw=0 /vexl=0</opc>
            <opr>V H Ed Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>


    <instruction>
        <mnemonic>vpinsrq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a 22 /m=64 /vexw=1 /vexl=0</opc>
            <opr>V H Eq Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>


    <instruction>
        <mnemonic>pmaddwd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f5</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f f5</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f ee</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f ee</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxub</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f de</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f de</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f ea</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f ea</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminub</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f da</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f da</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovmskb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>oso rexr rexw rexb vexl</pfx>
            <opc>/sse=66 0f d7</opc>
            <opr>Gd U</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>oso rexr rexw rexb vexl</pfx>
            <opc>0f d7</opc>
            <opr>Gd N</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmulhuw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e4</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e4</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmulhw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e5</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e5</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmullw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d5</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d5</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pop</mnemonic>
        <first_operand_access>W</first_operand_access>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>07 /m=!64</opc>
            <opr>ES</opr>
            <access source='scrape'>W</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>17 /m=!64</opc>
            <opr>SS</opr>
            <access source='scrape'>W</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>1f /m=!64</opc>
            <opr>DS</opr>
            <access source='scrape'>W</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>0f a9</opc>
            <opr>GS</opr>
            <access source='scrape'>W</access>
        </def>
        <def>
            <opc>0f a1</opc>
            <opr>FS</opr>
            <access source='scrape'>W</access>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>58</opc>
            <opr>R0v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>59</opc>
            <opr>R1v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5a</opc>
            <opr>R2v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5b</opc>
            <opr>R3v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5c</opc>
            <opr>R4v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5d</opc>
            <opr>R5v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5e</opc>
            <opr>R6v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>5f</opc>
            <opr>R7v</opr>
            <access source='scrape'>W</access>
            <mode>def64</mode>
        </def>
		
        <!-- borkes xop 
		<def> 
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>8f /reg=0</opc>
            <opr>Ev</opr>
			<access source='scrape'>W</access>
            <mode>def64</mode>
        </def>-->
		
    </instruction>

    <instruction>
        <mnemonic>popa</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>di</implicit_register_def>
        <implicit_register_def>si</implicit_register_def>
        <implicit_register_def>bp</implicit_register_def>
        <implicit_register_def>bx</implicit_register_def>
        <implicit_register_def>dx</implicit_register_def>
        <implicit_register_def>cx</implicit_register_def>
        <implicit_register_def>ax</implicit_register_def>
        <implicit_register_def>rbp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>61 /o=16 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>popad</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>edi</implicit_register_def>
        <implicit_register_def>esi</implicit_register_def>
        <implicit_register_def>ebp</implicit_register_def>
        <implicit_register_def>ebx</implicit_register_def>
        <implicit_register_def>edx</implicit_register_def>
        <implicit_register_def>ecx</implicit_register_def>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>rbp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>61 /o=32 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>popfw</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>PPPPPPPPPP__</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>9d /m=!64 /o=16</opc>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>9d /m=64 /o=16</opc>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>popfd</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>PPPPPPPPPP__</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>9d /m=!64 /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>popfq</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>PPPPPPPPPP__</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>9d /m=64 /o=32</opc>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>9d /m=64 /o=64</opc>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>por</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f eb</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f eb</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetch</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=0</opc>
            <opr>Mb</opr>
            <access source='manual'>R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=3</opc>
            <opr>Mb</opr>
			<access source='manual'>R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=4</opc>
            <opr>Mb</opr>
			<access source='manual'>R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=5</opc>
            <opr>Mb</opr>
			<access source='manual'>R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=6</opc>
            <opr>Mb</opr>
			<access source='manual'>R</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=7</opc>
            <opr>Mb</opr>
			<access source='manual'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetchnta</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 18 /reg=0</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetcht0</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 18 /reg=1</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetcht1</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 18 /reg=2</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetcht2</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 18 /reg=3</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetchw</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=1</opc>
            <opr>Mb</opr>
            <access source='manual'>R</access>
            <cpuid>prfchw</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>prefetchwt1</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f 0d /reg=2</opc>
            <opr>Mb</opr>
            <access source='scrape'>R</access>
            <cpuid>prefetchwt1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psadbw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f f6</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f6</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pshufw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 70</opc>
            <opr>P Q Ib</opr>
            <access source='scrape'>W R N</access>
        </def>
    </instruction>

     <instruction>
        <mnemonic>psllw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f f1</opc>
            <opr>V W</opr>
            <access source='manual'>RW R</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f1</opc>
            <opr>P Q</opr>
            <access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>/sse=66 0f 71 /reg=6</opc>
            <opr>U Ib</opr>
			<access source='manual'>RW N</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <opc>0f 71 /reg=6</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pslld</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f f2</opc>
            <opr>V W</opr>
			<access source='manual'>RW R</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f2</opc>
            <opr>P Q</opr>
			<access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>/sse=66 0f 72 /reg=6</opc>
            <opr>U Ib</opr>
			<access source='manual'>RW N</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <opc>0f 72 /reg=6</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psllq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f f3</opc>
            <opr>V W</opr>
			<access source='manual'>RW R</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f3</opc>
            <opr>P Q</opr>
			<access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>rexb</pfx>
            <opc>/sse=66 0f 73 /reg=6</opc>
            <opr>U Ib</opr>
			<access source='manual'>RW N</access>
            <cpuid>sse2</cpuid>
        </def>
        <def>
            <opc>0f 73 /reg=6</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psraw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e1</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e1</opc>
            <opr>V H MdqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 71 /reg=4</opc>
            <opr>H U Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <opc>0f 71 /reg=4</opc>
            <opr>N Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psrad</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <opc>0f 72 /reg=4</opc>
            <opr>N Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e2</opc>
            <opr>V H Wdq</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e2</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 72 /reg=4</opc>
            <opr>H U Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psrlw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <opc>0f 71 /reg=2</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d1</opc>
            <opr>P Q</opr>
			<access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d1</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 71 /reg=2</opc>
            <opr>H U Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psrld</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <opc>0f 72 /reg=2</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d2</opc>
            <opr>P Q</opr>
			<access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d2</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 72 /reg=2</opc>
            <opr>H U Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psrlq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <opc>0f 73 /reg=2</opc>
            <opr>N Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d3</opc>
            <opr>P Q</opr>
			<access source='manual'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d3</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 73 /reg=2</opc>
            <opr>H U Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f f8</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f8</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f f9</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f9</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f fa</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f fa</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubsb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e8</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e8</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f e9</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f e9</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubusb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d8</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d8</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubusw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d9</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d9</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpckhbw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 68</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 68</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpckhwd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 69</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 69</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpckhdq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 6a</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 6a</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpcklbw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 60</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 60</opc>
            <opr>P MdU</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpcklwd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 61</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 61</opc>
            <opr>P MdU</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpckldq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 62</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 62</opc>
            <opr>P MdU</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pi2fw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=0c</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pi2fd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=0d</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pf2iw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=1c</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pf2id</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=1d</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfnacc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=8a</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfpnacc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=8e</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfcmpge</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=90</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfmin</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=94</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfrcp</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=96</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfrsqrt</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=97</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfsub</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=9a</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfadd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=9e</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfcmpgt</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=a0</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfmax</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=a4</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfrcpit1</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=a6</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfrsqit1</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=a7</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfsubr</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=aa</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfacc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=ae</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfcmpeq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=b0</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfmul</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=b4</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pfrcpit2</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=b6</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmulhrw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=b7</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pswapd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=bb</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pavgusb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 0f /3dnow=bf</opc>
            <opr>P Q</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>push</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>06 /m=!64</opc>
            <opr>ES</opr>
            <access source='scrape'>R</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>0e /m=!64</opc>
            <opr>CS</opr>
            <access source='scrape'>R</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>16 /m=!64</opc>
            <opr>SS</opr>
            <access source='scrape'>R</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>1e /m=!64</opc>
            <opr>DS</opr>
            <access source='scrape'>R</access>
            <mode>inv64</mode>
        </def>
        <def>
            <opc>0f a8</opc>
            <opr>GS</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <opc>0f a0</opc>
            <opr>FS</opr>
            <access source='scrape'>R</access>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>50</opc>
            <opr>R0v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>51</opc>
            <opr>R1v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>52</opc>
            <opr>R2v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>53</opc>
            <opr>R3v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>54</opc>
            <opr>R4v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>55</opc>
            <opr>R5v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>56</opc>
            <opr>R6v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexb</pfx>
            <opc>57</opc>
            <opr>R7v</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>68</opc>
            <opr>sIz</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>ff /reg=6</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso</pfx>
            <opc>6a</opc>
            <opr>sIb</opr>
            <access source='scrape'>N</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pusha</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_use>cx</implicit_register_use>
        <implicit_register_use>dx</implicit_register_use>
        <implicit_register_use>bx</implicit_register_use>
        <implicit_register_use>bp</implicit_register_use>
        <implicit_register_use>si</implicit_register_use>
        <implicit_register_use>di</implicit_register_use>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>60 /o=16 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pushad</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>ecx</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>ebp</implicit_register_use>
        <implicit_register_use>esi</implicit_register_use>
        <implicit_register_use>edi</implicit_register_use>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>60 /o=32 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pushfw</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>TTTTTTTTTT__</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>9c /m=!64 /o=16</opc>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>9c /m=64 /o=16</opc>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pushfd</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>TTTTTTTTTT__</eflags>
        <def>
            <pfx>oso</pfx>
            <opc>9c /m=!64 /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pushfq</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <eflags source='scrape'>TTTTTTTTTT__</eflags>
        <def>
            <pfx>oso rexw</pfx>
            <opc>9c /m=64 /o=32</opc>
            <mode>def64</mode>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>9c /m=64 /o=64</opc>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pxor</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f ef</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f ef</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rcl</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>U____M______</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=2</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=2</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=2</opc>
            <opr>Eb I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=2</opc>
            <opr>Eb CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=2</opc>
            <opr>Ev CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=2</opc>
            <opr>Ev I1</opr>
			<access source='manual'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rcr</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>U____M______</eflags>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=3</opc>
            <opr>Eb I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=3</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=3</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=3</opc>
            <opr>Ev I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=3</opc>
            <opr>Eb CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=3</opc>
            <opr>Ev CL</opr>
			<access source='manual'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rol</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>U____M______</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=0</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=0</opc>
            <opr>Eb I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=0</opc>
            <opr>Ev I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=0</opc>
            <opr>Eb CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=0</opc>
            <opr>Ev CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=0</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ror</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>U____M______</eflags>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=1</opc>
            <opr>Eb I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=1</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=1</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
			<eflags source='manual'>M____M______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=1</opc>
            <opr>Ev I1</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=1</opc>
            <opr>Eb CL</opr>
			<access source='manual'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=1</opc>
            <opr>Ev CL</opr>
			<access source='manual'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rcpps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 53</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rcpss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 53</opc>
            <opr>V H MdU</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rdmsr</mnemonic>
        <implicit_register_use>ecx</implicit_register_use>
        <implicit_register_def>rdx</implicit_register_def>
        <implicit_register_def>rax</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rdpmc</mnemonic>
        <implicit_register_use>ecx</implicit_register_use>
        <implicit_register_def>rdx</implicit_register_def>
        <implicit_register_def>rax</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 33</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rdtsc</mnemonic>
        <implicit_register_def>rdx</implicit_register_def>
        <implicit_register_def>rax</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 31</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rdtscp</mnemonic>
        <implicit_register_def>ecx</implicit_register_def>
        <implicit_register_def>edx</implicit_register_def>
        <implicit_register_def>eax</implicit_register_def>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=7 /mod=11 /rm=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>repne</mnemonic>
        <implicit_register_use>rcx</implicit_register_use>
        <implicit_register_def>rcx</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>f2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rep</mnemonic>
        <implicit_register_use>rcx</implicit_register_use>
        <implicit_register_def>rcx</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>f3</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ret</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>c2</opc>
            <opr>Iw</opr>
            <access source='scrape'>N</access>
        </def>
        <def>
            <opc>c3</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>retf</mnemonic>
        <implicit_register_use>rsp</implicit_register_use>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <def>
            <opc>ca</opc>
            <opr>Iw</opr>
        </def>
        <def>
            <opc>cb</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rsm</mnemonic>
        <eflags source='scrape'>MMMMMMMMMMM_</eflags>
        <def>
            <opc>0f aa</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rsqrtps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 52</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rsqrtss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 52</opc>
            <opr>V H MdU</opr>
			<access source='manual'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sahf</mnemonic>
        <implicit_register_use>ah</implicit_register_use>
        <eflags source='scrape'>_PPPPP______</eflags>
        <def>
            <opc>9e</opc>
        </def>
    </instruction>

	<!-- Note: we decode SAL as SHL -->
    <instruction>
        <mnemonic>sal</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMUMM______</eflags>
    </instruction>

    <instruction>
        <mnemonic>salc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>_____T______</eflags>
        <def>
            <opc>d6 /m=!64</opc>
            <mode>inv64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sar</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>UMMUMM______</eflags>
        <def>
            <eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=7</opc>
            <opr>Ev I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=7</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=7</opc>
            <opr>Eb I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=7</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=7</opc>
            <opr>Eb CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=7</opc>
            <opr>Ev CL</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shl</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>UMMUMM______</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=6</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=6</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=6</opc>
            <opr>Eb I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=6</opc>
            <opr>Eb CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=6</opc>
            <opr>Ev CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=4</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>d2 /reg=4</opc>
            <opr>Eb CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=4</opc>
            <opr>Ev I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=4</opc>
            <opr>Eb I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=4</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=4</opc>
            <opr>Ev CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=6</opc>
            <opr>Ev I1</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shr</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>UMMUMM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>c1 /reg=5</opc>
            <opr>Ev Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d2 /reg=5</opc>
            <opr>Eb CL</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d1 /reg=5</opc>
            <opr>Ev I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
			<eflags source='manual'>MMMUMM______</eflags>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>d0 /reg=5</opc>
            <opr>Eb I1</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>c0 /reg=5</opc>
            <opr>Eb Ib</opr>
			<access source='manual'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>d3 /reg=5</opc>
            <opr>Ev CL</opr>
			<access source='manual'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sbb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>18</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>19</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>1a</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>1b</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <implicit_register_use>al</implicit_register_use>
            <implicit_register_def>al</implicit_register_def>
            <opc>1c</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <implicit_register_use>eax</implicit_register_use>
            <implicit_register_def>eax</implicit_register_def>
            <pfx>oso rexw</pfx>
            <opc>1d</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=3</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=3</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>W N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=3 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>W N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=3</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>W N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>scasb</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz</pfx>
            <opc>ae</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>scasw</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz oso rexw</pfx>
            <opc>af /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>scasd</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz oso rexw</pfx>
            <opc>af /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>scasq</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>MMMMMM__T___</eflags>
        <def>
            <pfx>repz oso rexw</pfx>
            <opc>af /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>seto</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>T___________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 90</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setno</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>T___________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 91</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>_____T______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 92</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setae</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>_____T______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 93</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sete</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 94</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setne</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='manual'>__T_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 95</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setbe</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>__T__T______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 96</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>seta</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>__T__T______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 97</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sets</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>_T__________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 98</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setns</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>_T__________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 99</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setp</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____T_______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9a</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setnp</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____T_______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9b</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setl</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>TT__________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9c</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setge</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>TT__________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9d</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setle</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>TTT_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9e</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>setg</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>TTT_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 9f</opc>
            <opr>Eb</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sfence</mnemonic>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=0</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=1</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=2</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=3</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=4</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=5</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=6</opc>
        </def>
        <def>
            <opc>0f ae /reg=7 /mod=11 /rm=7</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sgdt</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=0 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shld</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>UMMUMM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f a4</opc>
            <opr>Ev Gv Ib</opr>
            <access source='scrape'>W R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f a5</opc>
            <opr>Ev Gv CL</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shrd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>UMMUMM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ac</opc>
            <opr>Ev Gv Ib</opr>
            <access source='scrape'>W R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ad</opc>
            <opr>Ev Gv CL</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shufpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f c6</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>shufps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f c6</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sidt</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 01 /reg=1 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sldt</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 00 /reg=0</opc>
            <opr>MwRv</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>smsw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 01 /reg=4 /mod=!11</opc>
            <opr>MwRv</opr>
            <access source='scrape'>W</access>
        </def>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 01 /reg=4 /mod=11</opc>
            <opr>MwRv</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sqrtps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 51</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sqrtpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 51</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sqrtsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 51</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sqrtss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 51</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stac</mnemonic>
        <eflags source='manual'>___________S</eflags>
        <def>
            <opc>0f 01 /reg=1 /mod=11 /rm=3</opc>
			<cpuid>smap</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stc</mnemonic>
        <eflags source='scrape'>_____S______</eflags>
        <def>
            <opc>f9</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>std</mnemonic>
        <eflags source='scrape'>________S___</eflags>
        <def>
            <opc>fd</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stgi</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=4</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sti</mnemonic>
        <eflags source='scrape'>_______S____</eflags>
        <def>
            <opc>fb</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>skinit</mnemonic>
        <implicit_register_def>rax</implicit_register_def>
        <implicit_register_def>rbx</implicit_register_def>
        <implicit_register_def>rcx</implicit_register_def>
        <implicit_register_def>rdx</implicit_register_def>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <implicit_register_def>rbp</implicit_register_def>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>cr0</implicit_register_def>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=6</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stmxcsr</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /mod=!11 /reg=3</opc>
            <opr>Md</opr>
            <access source='scrape'>W</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stosb</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>________T___</eflags>
        <def>
            <pfx>rep seg</pfx>
            <opc>aa</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stosw</mnemonic>
        <implicit_register_use>ax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ab /o=16</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stosd</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ab /o=32</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>stosq</mnemonic>
        <implicit_register_use>rax</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rdi</implicit_register_def>
        <eflags source='manual'>________T___</eflags>
        <def>
            <pfx>rep seg oso rexw</pfx>
            <opc>ab /o=64</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>str</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 00 /reg=1</opc>
            <opr>MwRv</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sub</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>28</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>29</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>2a</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>2b</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>2c</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>2d</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=5</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=5</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=5 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=5</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>subpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 5c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>subps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 5c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>subsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 5c</opc>
            <opr>V H MqU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>subss</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 5c</opc>
            <opr>V H MdU</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>swapgs</mnemonic>
        <implicit_register_def>gs</implicit_register_def>
        <def>
            <opc>0f 01 /reg=7 /mod=11 /rm=0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>syscall</mnemonic>
        <implicit_register_use>rip</implicit_register_use>
        <implicit_register_def>rcx</implicit_register_def>
        <implicit_register_def>r11</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>MMMMMMMMMMM_</eflags>
        <def>
            <opc>0f 05</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sysenter</mnemonic>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>MMMMMMMMMMM_</eflags>
        <def>
            <opc>0f 34 /m=!64</opc>
        </def>
        <def>
            <opc>0f 34 /m=64</opc>
            <vendor>intel</vendor>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sysexit</mnemonic>
        <implicit_register_def>rsp</implicit_register_def>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>MMMMMMMMMMM_</eflags>
        <def>
            <opc>0f 35 /m=!64</opc>
        </def>
        <def>
            <opc>0f 35 /m=64</opc>
            <vendor>intel</vendor>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sysret</mnemonic>
        <implicit_register_use>rcx</implicit_register_use>
        <implicit_register_def>rip</implicit_register_def>
        <eflags source='scrape'>MMMMMMMMMMM_</eflags>
        <def>
            <opc>0f 07</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>test</mnemonic>
        <eflags source='scrape'>RMMUMR______</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=0</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>84</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>R R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>85</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>R R</access>
        </def>
        <def>
            <opc>a8</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>a9</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>f6 /reg=1</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=0</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>f7 /reg=1</opc>
            <opr>Ev Iz</opr>
            <access source='scrape'>R N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ucomisd</mnemonic>
        <eflags source='scrape'>RRMRMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 2e</opc>
            <opr>V MqU</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ucomiss</mnemonic>
        <eflags source='scrape'>RRMRMM______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 2e</opc>
            <opr>V MdU</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>ud1</mnemonic>
        <def>
            <opc>0f b9</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>ud2</mnemonic>
		<eflags source='manual'>____________</eflags>
        <def>
            <opc>0f 0b</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>unpckhpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 15</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>unpckhps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 15</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>unpcklps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 14</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>unpcklpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 14</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>verr</mnemonic>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 00 /reg=4</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>verw</mnemonic>
        <eflags source='scrape'>__M_________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 00 /reg=5</opc>
            <opr>Ew</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmcall</mnemonic>
        <vendor>intel</vendor>
        <def>
            <opc>0f 01 /reg=0 /mod=11 /rm=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>rdrand</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>oso rexr rexw rexx rexb</pfx>
            <opc>0f c7 /mod=11 /reg=6</opc>
            <opr>Rv</opr>
            <access source='scrape'>W</access>
        </def>
        <cpuid>rdrand</cpuid>
    </instruction>

    <instruction>
        <mnemonic>rdseed</mnemonic>
        <eflags source='manual'>RRRRRM______</eflags>
        <def>
            <pfx>oso rexr rexw rexx rexb</pfx>
            <opc>0F C7 /mod=11 /reg=7</opc>
            <opr>Ev</opr>
            <access source='scrape'>W</access>
        </def>
        <cpuid>rdseed</cpuid>
    </instruction>

    <instruction>
        <mnemonic>vmclear</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f c7 /mod=!11 /reg=6</opc>
            <opr>Mq</opr>
			<access source='manual'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmxon</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f c7 /mod=!11 /reg=6</opc>
            <opr>Mq</opr>
			<access source='manual'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmptrld</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f c7 /mod=!11 /reg=6</opc>
            <opr>Mq</opr>
			<access source='manual'>R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmptrst</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f c7 /mod=!11 /reg=7</opc>
            <opr>Mq</opr>
			<access source='manual'>W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmlaunch</mnemonic>
        <vendor>intel</vendor>
        <def>
            <opc>0f 01 /reg=0 /mod=11 /rm=2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmresume</mnemonic>
        <vendor>intel</vendor>
        <def>
            <opc>0f 01 /reg=0 /mod=11 /rm=3</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmxoff</mnemonic>
        <vendor>intel</vendor>
        <def>
            <opc>0f 01 /reg=0 /mod=11 /rm=4</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmread</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 78</opc>
            <opr>Ey Gy</opr>
			<access source='manual'>W R</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmwrite</mnemonic>
        <vendor>intel</vendor>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 79</opc>
            <opr>Gy Ey</opr>
			<access source='manual'>W R</access>
            <mode>def64</mode>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmrun</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmmcall</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmload</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmsave</mnemonic>
        <vendor>amd</vendor>
        <def>
            <opc>0f 01 /reg=3 /mod=11 /rm=3</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>wait</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>9b</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>wbinvd</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 09</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>wrmsr</mnemonic>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>eax</implicit_register_use>
        <eflags source='scrape'>____________</eflags>
        <def>
            <opc>0f 30</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xadd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <second_operand_access>W</second_operand_access>
        <eflags source='scrape'>MMMMMM______</eflags>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>0f c0</opc>
            <opr>Eb Gb</opr>
			<access source='manual'>RW W</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f c1</opc>
            <opr>Ev Gv</opr>
			<access source='manual'>RW W</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xchg</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <second_operand_access>RW</second_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>86</opc>
            <opr>Eb Gb</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>87</opc>
            <opr>Ev Gv</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>90</opc>
            <opr>R0v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>91</opc>
            <opr>R1v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>92</opc>
            <opr>R2v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>93</opc>
            <opr>R3v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>94</opc>
            <opr>R4v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>95</opc>
            <opr>R5v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>96</opc>
            <opr>R6v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>97</opc>
            <opr>R7v rAX</opr>
			<access source='manual'>RW RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xgetbv</mnemonic>
        <implicit_register_use>ecx</implicit_register_use>
        <implicit_register_def>edx</implicit_register_def>
        <implicit_register_def>eax</implicit_register_def>
    <def>
        <opc>0f 01 /mod=11 /reg=2 /rm=0</opc>
    </def>
    </instruction>

    <instruction>
        <mnemonic>xlatb</mnemonic>
        <implicit_register_use>al</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_def>al</implicit_register_def>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>rexw seg</pfx>
            <opc>d7</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xor</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>RMMUMR______</eflags>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>30</opc>
            <opr>Eb Gb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>31</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>32</opc>
            <opr>Gb Eb</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>33</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <opc>34</opc>
            <opr>AL Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>oso rexw</pfx>
            <opc>35</opc>
            <opr>rAX sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>80 /reg=6</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>81 /reg=6</opc>
            <opr>Ev sIz</opr>
            <access source='scrape'>RW N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>82 /reg=6 /m=!64</opc>
            <opr>Eb Ib</opr>
            <access source='scrape'>RW N</access>
            <mode>inv64</mode>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>83 /reg=6</opc>
            <opr>Ev sIb</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xorpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 57</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xorps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>0f 57</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xcryptecb</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xcryptcbc</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xcryptctr</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=3</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xcryptcfb</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=4</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xcryptofb</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>ebx</implicit_register_use>
        <implicit_register_use>rsi</implicit_register_use>
        <implicit_register_use>rdi</implicit_register_use>
        <implicit_register_def>rsi</implicit_register_def>
        <implicit_register_def>rdi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=5</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xrstor</mnemonic>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>eax</implicit_register_use>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /reg=5 /mod=!11</opc>
            <opr>M</opr>
			<access source='scrape'>R</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xsave</mnemonic>
        <implicit_register_def>edx</implicit_register_def>
        <implicit_register_def>eax</implicit_register_def>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /reg=4 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>
    <instruction>
        <mnemonic>xsaveopt</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0f ae /reg=6 /mod=!11</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xsetbv</mnemonic>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>eax</implicit_register_use>
        <def>
          <opc>0f 01 /mod=11 /reg=2 /rm=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xsha1</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>esi</implicit_register_use>
        <implicit_register_use>edi</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>esi</implicit_register_def>
        <implicit_register_def>edi</implicit_register_def>
        <def>
            <opc>0f a6 /mod=11 /rm=0 /reg=1</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xsha256</mnemonic>
        <implicit_register_use>eax</implicit_register_use>
        <implicit_register_use>esi</implicit_register_use>
        <implicit_register_use>edi</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>esi</implicit_register_def>
        <implicit_register_def>edi</implicit_register_def>
        <def>
            <opc>0f a6 /mod=11 /rm=0 /reg=2</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xstore</mnemonic>
        <implicit_register_use>edx</implicit_register_use>
        <implicit_register_use>edi</implicit_register_use>
        <implicit_register_def>eax</implicit_register_def>
        <implicit_register_def>edi</implicit_register_def>
        <def>
            <opc>0f a7 /mod=11 /rm=0 /reg=0</opc>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pclmulqdq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 44</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>aesni avx</cpuid>
        </def>
    </instruction>

    <!--
    SMX
      -->

    <instruction>
        <mnemonic>getsec</mnemonic>
    <cpuid>smx</cpuid>
    <def>
        <opc>0f 37</opc>
    </def>
    </instruction>

    <!--
         SSE 2
     -->

    <instruction>
        <mnemonic>movdqa</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 7f</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 6f</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
        </def>
        <cpuid>sse2 avx</cpuid>
    </instruction>

    <instruction>
        <mnemonic>maskmovdqu</mnemonic>
        <implicit_register_use>rdi</implicit_register_use>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f f7 /mod=11</opc>
            <opr>V U</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movdq2q</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexb</pfx>
            <opc>/sse=f2 0f d6</opc>
            <opr>P U</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movdqu</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 6f</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 7f</opc>
            <opr>W V</opr>
            <access source='scrape'>W R</access>
        </def>
		<cpuid>sse2 avx</cpuid>
    </instruction>

    <instruction>
        <mnemonic>movq2dq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr</pfx>
            <opc>/sse=f3 0f d6</opc>
            <opr>V N</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>paddq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f d4</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f d4</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psubq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f fb</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f fb</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmuludq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f f4</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f f4</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
			<cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pshufhw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 70</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pshuflw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f2 0f 70</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pshufd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 70</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pslldq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 73 /reg=7</opc>
            <opr>H U Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psrldq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>rexb vexl</pfx>
            <opc>/sse=66 0f 73 /reg=3</opc>
            <opr>H U Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpckhqdq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 6d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>punpcklqdq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 6c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>haddpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 7c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>haddps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f2 0f 7c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>hsubpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 7d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>hsubps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f2 0f 7d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>insertps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 21</opc>
            <opr>V H MdU Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>lddqu</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexr rexx rexb vexl</pfx>
            <opc>/sse=f2 0f f0</opc>
            <opr>V M</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>movddup</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 12 /mod=!11</opc>
            <opr>V W</opr>
			<access source='manual'>W R</access>
        </def>
        <cpuid>sse3</cpuid>
    </instruction>

    <instruction>
        <mnemonic>vmovddup</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=f2_0f 12 /vexl=0</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=f2_0f 12 /vexl=1</opc>
            <opr>V W</opr>
			<access source='manual'>W R</access>
        </def>
        <cpuid>avx</cpuid>
    </instruction>

    <instruction>
        <mnemonic>movshdup</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 16 /mod=11</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 16 /mod=!11</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movsldup</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 12 /mod=11</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=f3 0f 12 /mod=!11</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 avx</cpuid>
        </def>
    </instruction>

    <!--
         SSSE 3
     -->

    <instruction>
        <mnemonic>pabsb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 1c</opc>
            <opr>P Q</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 1c</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pabsw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 1d</opc>
            <opr>P Q</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 1d</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pabsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 1e</opc>
            <opr>P Q</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 1e</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pshufb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 00</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 00</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phaddw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 01</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 01</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phaddd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 02</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 02</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phaddsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 03</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 03</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaddubsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 04</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 04</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phsubw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 05</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 05</opc>
            <opr>V H W</opr>
            <access source='scrape'>RW R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phsubd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 06</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 06</opc>
            <opr>V H W</opr>
            <access source='scrape'>RW R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phsubsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 07</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 07</opc>
            <opr>V H W</opr>
            <access source='scrape'>RW R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psignb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 08</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 08</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psignd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 0a</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 0a</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>psignw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 09</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 09</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmulhrsw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 38 0b</opc>
            <opr>P Q</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 0b</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>palignr</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>0f 3a 0f</opc>
            <opr>P Q Ib</opr>
            <access source='scrape'>RW R N</access>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 0f</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>ssse3 avx</cpuid>
        </def>
    </instruction>

    <!--
         SSE 4.1
     -->

    <instruction>
        <mnemonic>pblendvb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 10</opc>
            <opr>V W IMP_XMM0</opr>
			<access source='manual'>RW R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmuldq</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 28</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminsb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 38</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 39</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminuw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3a</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pminud</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3b</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxsb</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3c</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxsd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3d</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxud</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3f</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmaxuw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 3e</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmulld</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 40</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>phminposuw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 41</opc>
            <opr>V W</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>roundps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 08</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>roundpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 09</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>roundss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 0a</opc>
            <opr>V H MdU Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>roundsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 3a 0b</opc>
            <opr>V H MqU Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>blendpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 0d</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>blendps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 0c</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>blendvpd</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 15</opc>
            <opr>V W IMP_XMM0</opr>
			<access source='manual'>RW R R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>blendvps</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 38 14</opc>
            <opr>V W IMP_XMM0</opr>
			<access source='manual'>RW R R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bound</mnemonic>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>aso oso</pfx>
            <opc>62 /m=!64</opc>
            <opr>Gv M</opr>
            <access source='scrape'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bsf</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>UUMUUU______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f bc</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bsr</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>UUMUUU______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f bd</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bswap</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='scrape'>____________</eflags>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f c8</opc>
            <opr>R0y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f c9</opc>
            <opr>R1y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f ca</opc>
            <opr>R2y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f cb</opc>
            <opr>R3y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f cc</opc>
            <opr>R4y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f cd</opc>
            <opr>R5y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f ce</opc>
            <opr>R6y</opr>
            <access source='scrape'>RW</access>
        </def>
        <def>
            <pfx>oso rexw rexb</pfx>
            <opc>0f cf</opc>
            <opr>R7y</opr>
            <access source='scrape'>RW</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bt</mnemonic>
        <eflags source='manual'>UU_UUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ba /reg=4</opc>
            <opr>Ev Ib</opr>
            <access source='scrape'>R N</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f a3</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>btc</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>UU_UUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f bb</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ba /reg=7</opc>
            <opr>Ev Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>btr</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>UU_UUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f b3</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ba /reg=6</opc>
            <opr>Ev Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bts</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <eflags source='manual'>UU_UUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ab</opc>
            <opr>Ev Gv</opr>
            <access source='scrape'>RW R</access>
        </def>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>0f ba /reg=5</opc>
            <opr>Ev Ib</opr>
            <access source='scrape'>RW N</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pblendw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 0e</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>mpsadbw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/sse=66 0f 3a 42</opc>
            <opr>V H W Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntdqa</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 2a</opc>
            <opr>V Mx</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>packusdw</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 2b</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse2 avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>pmovsxbw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 20</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxbw</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 20 /vexl=0</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 20 /vexl=1</opc>
            <opr>V MdqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>pmovsxbd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 21</opc>
            <opr>V MdU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxbd</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 21 /vexl=0</opc>
            <opr>V MdU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 21 /vexl=1</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>pmovsxbq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 22</opc>
            <opr>V MwU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxbq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 22 /vexl=0</opc>
            <opr>V MwU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 22 /vexl=1</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovsxwd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 23</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxwd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 23 /vexl=0</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 23 /vexl=1</opc>
            <opr>V MdqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovsxwq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 24</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxwq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 24 /vexl=0</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 24 /vexl=1</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovsxdq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 25</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovsxdq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 25 /vexl=0</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 25 /vexl=1</opc>
            <opr>V MdqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxbw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 30</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxbw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 30 /vexl=0</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 30 /vexl=1</opc>
            <opr>V MdqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxbd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 31</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxbd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 31 /vexl=0</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 31 /vexl=1</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxbq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 32</opc>
            <opr>V MwU</opr>
            <access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxbq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 32 /vexl=0</opc>
            <opr>V MwU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 32 /vexl=1</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxwd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 33</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxwd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 33 /vexl=0</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 33 /vexl=1</opc>
            <opr>V MdqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxwq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 34</opc>
            <opr>V MdU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxwq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 34 /vexl=0</opc>
            <opr>V MdU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 34 /vexl=1</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pmovzxdq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 35</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>sse4.1</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmovzxdq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 35 /vexl=0</opc>
            <opr>V MqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 35 /vexl=1</opc>
            <opr>V MdqU</opr>
			<access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpeqq</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 29</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

     <instruction>
        <mnemonic>popcnt</mnemonic>
        <first_operand_access>W</first_operand_access>
        <eflags source='scrape'>RRMRRR______</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=f3 0f b8</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
        </def>
        <cpuid>sse4.2</cpuid>
    </instruction>

    <instruction>
        <mnemonic>ptest</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 17</opc>
            <opr>V W</opr>
            <access source='scrape'>R R</access>
            <cpuid>sse4.1 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpestri</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 61</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>R R N</access>
            <cpuid>sse4.2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpestrm</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 60</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>R R N</access>
            <cpuid>sse4.2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpgtq</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb vexl</pfx>
            <opc>/sse=66 0f 38 37</opc>
            <opr>V H W</opr>
            <access source='scrape'>W R R</access>
            <cpuid>sse4.2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpistri</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 63</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>R R N</access>
            <cpuid>sse4.2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>pcmpistrm</mnemonic>
        <def>
            <pfx>aso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 3a 62</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>R R N</access>
            <cpuid>sse4.2 avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movbe</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 38 f0</opc>
            <opr>Gv Mv</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 atom</cpuid>
        </def>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 38 f1</opc>
            <opr>Mv Gv</opr>
            <access source='scrape'>W R</access>
            <cpuid>sse3 atom</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>crc32</mnemonic>
        <first_operand_access>RW</first_operand_access>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=f2 0f 38 f0</opc>
            <opr>Gy Eb</opr>
            <access source='scrape'>RW R</access>
            <cpuid>sse4.2</cpuid>
        </def>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=f2 0f 38 f1</opc>
            <opr>Gy Ev</opr>
            <access source='scrape'>RW R</access>
            <cpuid>sse4.2</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invalid</mnemonic>
    </instruction>

    <instruction>
        <mnemonic>vbroadcastss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 18 /vexw=0</opc>
            <opr>V MdU</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vbroadcastsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 19 /vexw=0 /vexl=1</opc>
            <opr>Vqq MqU</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmaskmovq</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 8c /vexw=1</opc>
            <opr>V H M</opr>
            <access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 8e /vexw=1</opc>
            <opr>M H V</opr>
            <access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vextractf128</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 19 /vexw=0 /vexl=1</opc>
            <opr>Wdq Vqq Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vinsertf128</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 18 /vexw=0 /vexl=1</opc>
            <opr>Vqq Hqq Wdq Ib</opr>
			<access source='manual'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vmaskmovps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 2c /vexw=0</opc>
            <opr>V H M</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 2e /vexw=0</opc>
            <opr>M H V</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmaskmovpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <cpuid>avx</cpuid>
        <def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 2d /vexw=0</opc>
            <opr>Vx Hx Mx</opr>
            <access source='scrape'>W R R</access>
        </def>
        <def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 2f /vexw=0</opc>
            <opr>Mx Hx Vx</opr>
            <access source='scrape'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vbroadcastf128</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 1a /vexw=0 /vexl=1</opc>
            <opr>Vqq Mdq</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpblendd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 02 /vexw=0</opc>
            <opr>V H W Ib</opr>
            <access source='manual'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpermilpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 0d /vexw=0</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 05 /vexw=0</opc>
            <opr>V W Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpmaskmovd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 8c /vexw=0</opc>
            <opr>V H M</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 8e /vexw=0</opc>
            <opr>M H V</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpermilps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 0c /vexw=0</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 04 /vexw=0</opc>
            <opr>Vx Wx Ib</opr>
            <access source='scrape'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vperm2f128</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 06 /vexl=1 /vexw=0</opc>
            <opr>Vqq Hqq Wqq Ib</opr>
            <access source='scrape'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vtestps</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 0e /vexw=0</opc>
            <opr>Vx Wx</opr>
            <access source='scrape'>R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vtestpd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 0f /vexw=0</opc>
            <opr>Vx Wx</opr>
            <access source='scrape'>R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vextracti128</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 39 /vexl=1 /vexw=0</opc>
            <opr>MdqU Vqq Ib</opr>
            <access source='manual'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vinserti128</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 38 /vexl=1 /vexw=0</opc>
            <opr>Vqq H MdqU Ib</opr>
            <access source='manual'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vzeroupper</mnemonic>
        <implicit_register_def>ymm0</implicit_register_def>
        <implicit_register_def>ymm1</implicit_register_def>
        <implicit_register_def>ymm2</implicit_register_def>
        <implicit_register_def>ymm3</implicit_register_def>
        <implicit_register_def>ymm4</implicit_register_def>
        <implicit_register_def>ymm5</implicit_register_def>
        <implicit_register_def>ymm6</implicit_register_def>
        <implicit_register_def>ymm7</implicit_register_def>
        <implicit_register_def>ymm8</implicit_register_def>
        <implicit_register_def>ymm9</implicit_register_def>
        <implicit_register_def>ymm10</implicit_register_def>
        <implicit_register_def>ymm11</implicit_register_def>
        <implicit_register_def>ymm12</implicit_register_def>
        <implicit_register_def>ymm13</implicit_register_def>
        <implicit_register_def>ymm14</implicit_register_def>
        <implicit_register_def>ymm15</implicit_register_def>
        <def>
            <opc>/vex=0f 77 /vexl=0</opc>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vzeroall</mnemonic>
        <implicit_register_def>ymm0</implicit_register_def>
        <implicit_register_def>ymm1</implicit_register_def>
        <implicit_register_def>ymm2</implicit_register_def>
        <implicit_register_def>ymm3</implicit_register_def>
        <implicit_register_def>ymm4</implicit_register_def>
        <implicit_register_def>ymm5</implicit_register_def>
        <implicit_register_def>ymm6</implicit_register_def>
        <implicit_register_def>ymm7</implicit_register_def>
        <implicit_register_def>ymm8</implicit_register_def>
        <implicit_register_def>ymm9</implicit_register_def>
        <implicit_register_def>ymm10</implicit_register_def>
        <implicit_register_def>ymm11</implicit_register_def>
        <implicit_register_def>ymm12</implicit_register_def>
        <implicit_register_def>ymm13</implicit_register_def>
        <implicit_register_def>ymm14</implicit_register_def>
        <implicit_register_def>ymm15</implicit_register_def>
        <def>
            <opc>/vex=0f 77 /vexl=1</opc>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vperm2i128</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 46 /vexl=1 /vexw=0</opc>
            <opr>Vqq H Wqq Ib</opr>
            <access source='manual'>W R R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpsrlvd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 45 /vexw=0</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vpsrlvq</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 45 /vexw=1</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vpsravd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 46 /vexw=0</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpsllvd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 47 /vexw=0</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vpsllvq</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 47 /vexw=1</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	

    <instruction>
        <mnemonic>vpermpd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 01 /vexl=1 /vexw=1</opc>
            <opr>V W Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpermps</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 16 /vexl=1 /vexw=0</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpermd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 36 /vexl=1 /vexw=0</opc>
            <opr>V H W</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpermq</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 00 /vexl=1 /vexw=1</opc>
            <opr>V W Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vgatherdpd</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 92 /vexw=1</opc>
            <opr>V XSXq H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vgatherqpd</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 93 /vexw=1</opc>
            <opr>V XSq H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vgatherdps</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 92 /vexw=0</opc>
            <opr>V XSd H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vgatherqps</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 93 /vexw=0</opc>
            <opr>Vdq XSd Hdq</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpgatherdd</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 90 /vexw=0</opc>
            <opr>V XSd H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vpgatherqd</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 91 /vexw=0</opc>
            <opr>Vdq XSd Hdq</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	

    <instruction>
        <mnemonic>vpgatherdq</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 90 /vexw=1</opc>
            <opr>V XSXq H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vpgatherqq</mnemonic>
        <def>
            <pfx>rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 91 /vexw=1</opc>
            <opr>V XSq H</opr>
			<access source='manual'>RW R RW</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vblendvpd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 4b /vexw=0</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vblendvps</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 4a /vexw=0</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmovsd</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f2_0f 10 /mod=11</opc>
            <opr>V H U</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f2_0f 10 /mod=!11</opc>
            <opr>V Mq</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f2_0f 11 /mod=11</opc>
            <opr>U H V</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f2_0f 11 /mod=!11</opc>
            <opr>Mq V</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vmovss</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f3_0f 10 /mod=11</opc>
            <opr>V H U</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f3_0f 10 /mod=!11</opc>
            <opr>V Md</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f3_0f 11 /mod=11</opc>
            <opr>U H V</opr>
            <access source='scrape'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb</pfx>
            <opc>/vex=f3_0f 11 /mod=!11</opc>
            <opr>Md V</opr>
            <access source='scrape'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpblendvb</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f3a 4c /vexw=0</opc>
            <opr>V H W Lx</opr>
			<access source='manual'>W R R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpbroadcastb</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 78 /vexw=0</opc>
            <opr>V MbU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpbroadcastw</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 79 /vexw=0</opc>
            <opr>V MwU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpbroadcastd</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 58 /vexw=0</opc>
            <opr>V MdU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpbroadcastq</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 59 /vexw=0</opc>
            <opr>V MqU</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vbroadcasti128</mnemonic>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f38 5A /vexl=1 /vexw=0</opc>
            <opr>V Mdq</opr>
            <access source='manual'>W R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpsllw</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f f1</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f 71 /reg=6</opc>
            <opr>H W Ib</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

     <instruction>
        <mnemonic>vpslld</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f f2</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f 72 /reg=6</opc>
            <opr>H W Ib</opr>
			<access source='manual'>W R N</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>

      <instruction>
        <mnemonic>vpsllq</mnemonic>
        <first_operand_access>W</first_operand_access>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f f3</opc>
            <opr>V H MdqU</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
        <def>
            <pfx>aso rexr rexx rexb vexl</pfx>
            <opc>/vex=66_0f 73 /reg=6</opc>
            <opr>H W Ib</opr>
			<access source='manual'>W R R</access>
            <cpuid>avx</cpuid>
        </def>
    </instruction>
    <!-- ****************** BEGIN CUSTOM RELYZE EXTENSTIONS -->
	
	<instruction>
        <mnemonic>adox</mnemonic>
        <eflags source='manual'>M___________</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=f3 0F 38 F6</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
			<cpuid>adx</cpuid>
        </def>
	</instruction>
	
    <instruction>
        <mnemonic>adcx</mnemonic>
        <eflags source='manual'>_____M______</eflags>
        <def>
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0F 38 F6</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>RW R</access>
			<cpuid>adx</cpuid>
        </def>
	</instruction>
	
    <instruction>
        <mnemonic>lzcnt</mnemonic>
        <eflags source='manual'>UUMUUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F BD</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
			<cpuid>lzcnt</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>andn</mnemonic>
        <eflags source='manual'>RMMUUR______</eflags>
		<cpuid>avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F2</opc>
            <opr>Gd HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F2</opc>
            <opr>Gq HRq Eq</opr>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>bextr</mnemonic>
        <eflags source='manual'>RUMUURRRRRR_</eflags>
		<cpuid>avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F7</opc>
            <opr>Gd Ed HRd</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F7</opc>
            <opr>Gq Eq HRq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blsi</mnemonic>
        <eflags source='manual'>RMMUUM______</eflags>
		<cpuid>avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F3 /reg=3</opc>
            <opr>HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F3 /reg=3</opc>
            <opr>HRq Eq</opr>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blsmsk</mnemonic>
        <eflags source='manual'>RMRUUM______</eflags>
		<cpuid>avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F3 /reg=2</opc>
            <opr>HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F3 /reg=2</opc>
            <opr>HRq Eq</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>blsr</mnemonic>
        <eflags source='manual'>RMRUUM______</eflags>
		<cpuid>avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F3 /reg=1</opc>
            <opr>HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F3 /reg=1</opc>
            <opr>HRq Eq</opr>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>tzcnt</mnemonic>
        <eflags source='manual'>UUMUUM______</eflags>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F BC</opc>
            <opr>Gv Ev</opr>
            <access source='scrape'>W R</access>
			<cpuid>bmi1</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>bzhi</mnemonic>
        <eflags source='manual'>RMMUUM______</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=0 F5</opc>
            <opr>Gd Ed HRd</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f38 /vexl=0 /vexw=1 F5</opc>
            <opr>Gq Eq HRq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>mulx</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=0 F6</opc>
            <opr>Gd HRd Ed</opr>
			<access source='manual'>W W R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=1 F6</opc>
            <opr>Gq HRq Eq</opr>
			<access source='manual'>W W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>pdep</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=0 F5</opc>
            <opr>Gd HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=1 F5</opc>
            <opr>Gq HRq Eq</opr>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>pext</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f3_0f38 /vexl=0 /vexw=0 F5</opc>
            <opr>Gd HRd Ed</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f3_0f38 /vexl=0 /vexw=1 F5</opc>
            <opr>Gq HRq Eq</opr>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>rorx</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f3a /vexl=0 /vexw=0 F0</opc>
            <opr>Gd Ed Ib</opr>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f3a /vexl=0 /vexw=1 F0</opc>
            <opr>Gq Eq Ib</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>sarx</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f3_0f38 /vexl=0 /vexw=0 F7</opc>
            <opr>Gd Ed HRd</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f3_0f38 /vexl=0 /vexw=1 F7</opc>
            <opr>Gq Eq HRq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>shlx</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexl=0 /vexw=0 F7</opc>
            <opr>Gd Ed HRd</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexl=0 /vexw=1 F7</opc>
            <opr>Gq Eq HRq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>shrx</mnemonic>
        <eflags source='manual'>____________</eflags>
		<cpuid>avx bmi2</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=0 F7</opc>
            <opr>Gd Ed HRd</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f38 /vexl=0 /vexw=1 F7</opc>
            <opr>Gq Eq HRq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vcvtph2ps</mnemonic>
		<cpuid>avx f16c</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexl=1 /vexw=0 13</opc>
            <opr>Vqq Wx</opr>
            <access source='scrape'>W R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexl=0 /vexw=0 13</opc>
            <opr>Vx MqU</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>vcvtps2ph</mnemonic>
		<cpuid>avx f16c</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=1 /vexw=0 1d</opc>
            <opr>Wx Vqq Ib</opr>
			<access source='manual'>W R N</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=0 1d</opc>
            <opr>MqU Vx Ib</opr>
			<access source='manual'>W R N</access>
        </def>
    </instruction>
	
	<instruction><mnemonic>xsave64</mnemonic><def/></instruction>

    <instruction>
        <mnemonic>xsavec</mnemonic>
        <eflags source='manual'>____________</eflags>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0F C7 /mod=!11 /reg=4</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>
	
	<instruction><mnemonic>xsavec64</mnemonic><def/></instruction>

	<instruction><mnemonic>xsaveopt64</mnemonic><def/></instruction>

    <instruction>
        <mnemonic>xsaves</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0F C7 /mod=!11 /reg=5</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>
	
	<instruction><mnemonic>xsaves64</mnemonic><def/></instruction>

	<instruction><mnemonic>xrstor64</mnemonic><def/></instruction>

    <instruction>
        <mnemonic>xrstors</mnemonic>
        <def>
            <pfx>aso rexw rexr rexx rexb</pfx>
            <opc>0F C7 /mod=!11 /reg=3</opc>
            <opr>M</opr>
            <access source='scrape'>R</access>
			<cpuid>xsave</cpuid>
        </def>
    </instruction>
	
	<instruction><mnemonic>xrstors64</mnemonic><def/></instruction>

    <instruction>
        <mnemonic>rdfsbase</mnemonic>
        <def>
            <pfx>oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=0</opc>
            <opr>Ev</opr>
            <access source='scrape'>W</access>
			<cpuid>fsgsbase</cpuid>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>rdgsbase</mnemonic>
        <def>
            <pfx>oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=1</opc>
            <opr>Ev</opr>
            <access source='scrape'>W</access>
			<cpuid>fsgsbase</cpuid>
        </def>
    </instruction>
 	
    <instruction>
        <mnemonic>wrfsbase</mnemonic>
        <def>
            <pfx>oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=2</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
			<cpuid>fsgsbase</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>wrgsbase</mnemonic>
        <def>
            <pfx>oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=3</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
			<cpuid>fsgsbase</cpuid>
        </def>
    </instruction>
	
	<!-- a MOV encoding collides so we adjust it with: "<opc>c6 /mod=!11 /reg=0</opc>" -->
    <instruction>
        <mnemonic>xabort</mnemonic>
        <def>
            <opc>c6 /mod=11 /reg=7 /rm=0</opc>
            <opr>Ib</opr>
            <access source='scrape'>N</access>
			<cpuid>rtm</cpuid>
        </def>
    </instruction>

	<!-- a MOV encoding collides so we adjust it with: "<opc>c7 /mod=!11 /reg=0</opc>" -->
    <instruction>
        <mnemonic>xbegin</mnemonic>
        <def>
			<pfx>aso</pfx>
            <opc>c7 /mod=11 /reg=7 /rm=0</opc>
			<opr>Jz</opr>
			<access source='manual'>N</access>
			<cpuid>rtm</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>xend</mnemonic>
        <def>
            <opc>0f 01 /mod=11 /reg=2 /rm=5</opc>
			<cpuid>rtm</cpuid>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>xtest</mnemonic>
        <def>
            <opc>0f 01 /mod=11 /reg=2 /rm=6</opc>
			<cpuid>rtm</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>invpcid</mnemonic>
		<cpuid>invpcid</cpuid>
        <def>
            <opc>/sse=66 0F 38 82 /m=!64</opc>
			<opr>Gv W</opr>
			<access source='manual'>R R</access>
        </def>
        <def>
            <opc>/sse=66 0F 38 82 /m=64</opc>
			<opr>Gq W</opr>
			<access source='manual'>R R</access>
			<mode>def64</mode>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vmfunc</mnemonic>
		<vendor>intel</vendor>
        <def>
            <opc>0f 01 /mod=11 /reg=2 /rm=4</opc>
			<cpuid>vmx</cpuid>
        </def>
    </instruction>   

	<instruction>
        <mnemonic>encls</mnemonic>
		<vendor>intel</vendor>
        <def>
            <opc>0f 01 /mod=11 /reg=1 /rm=7</opc>
			<cpuid>sgx1</cpuid>
        </def>
    </instruction>
	
	<instruction>
        <mnemonic>enclu</mnemonic>
		<vendor>intel</vendor>
        <def>
            <opc>0f 01 /mod=11 /reg=2 /rm=7</opc>
			<cpuid>sgx1</cpuid>
        </def>
    </instruction>
	
	<instruction>
        <mnemonic>sha1rnds4</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 3a cc</opc>
			<opr>V W Ib</opr>
			<access source='manual'>RW R N</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>
	
	<instruction>
        <mnemonic>sha1nexte</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 c8</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>	
	
	<instruction>
        <mnemonic>sha1msg1</mnemonic>
		<vendor>intel</vendor>
        <def>	
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 c9</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>	
	
	<instruction>
        <mnemonic>sha1msg2</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 ca</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>
	
	<instruction>
        <mnemonic>sha256rnds2</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 cb</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>	
	
	<instruction>
        <mnemonic>sha256msg1</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 cc</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>
	
	<instruction>
        <mnemonic>sha256msg2</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>0f 38 cd</opc>
			<opr>V W</opr>
			<access source='manual'>RW R</access>
			<cpuid>sha</cpuid>
        </def>
    </instruction>

	<instruction>
        <mnemonic>clflushopt</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f ae /mod=!11 /reg=7</opc>
			<opr>Mb</opr>
			<access source='manual'>R</access>
			<cpuid>clflushopt</cpuid>
        </def>
    </instruction>	

	<!-- Note: a table lookup fails for some reason
	<instruction>
        <mnemonic>clwb</mnemonic>
		<vendor>intel</vendor>
        <def>
			<pfx>rexw rexr rexx rexb</pfx>
            <opc>/sse=66 0f ae /mod=!11 /reg=6</opc>
			<opr>Mb</opr>
			<cpuid>clwb</cpuid>
        </def>
    </instruction>-->	
	
	<instruction>
        <mnemonic>pcommit</mnemonic>
		<vendor>intel</vendor>
        <def>
            <opc>/sse=66 0f ae /mod=11 /reg=7 /rm=0</opc>
			<cpuid>pcommit</cpuid>
        </def>
    </instruction>

	<!-- These are placeholders so decode.c can fixup a PCLMULQDQ instruction:
		 http://en.wikipedia.org/wiki/CLMUL_instruction_set -->
	<instruction>
		<mnemonic>pclmullqlqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>pclmulhqlqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>pclmullqhqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>pclmulhqhqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>vpclmullqlqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>vpclmulhqlqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>vpclmullqhqdq</mnemonic><def/>
    </instruction>

	<instruction>
		<mnemonic>vpclmulhqhqdq</mnemonic><def/>
    </instruction>

    <instruction>
        <mnemonic>vfmadd132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 98</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 a8</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 b8</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 98</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 a8</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 b8</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd132sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 99</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd213sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 a9</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd231sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 b9</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd132ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 99</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd213ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 a9</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmadd231ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 b9</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 96</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 a6</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 b6</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 96</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 a6</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsub231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 b6</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9a</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 aa</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 ba</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9a</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 aa</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 ba</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub132sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9b</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfmsub213sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 ab</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfmsub231sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 bb</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubadd132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 97</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfmsubadd213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 a7</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfmsubadd231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 b7</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubadd132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 97</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfmsubadd213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 a7</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfmsubadd231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 b7</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmadd132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9c</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmadd213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 ac</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmadd231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 bc</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmadd132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9c</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmadd213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 ac</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmadd231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 bc</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmadd132sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9d</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmadd213sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 ad</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmadd231sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 bd</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmadd132ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9d</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmadd213ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 ad</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmadd231ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 bd</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsub132pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9e</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmsub213pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 ae</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmsub231pd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 be</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsub132ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9e</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmsub213ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 ae</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	 <instruction>
        <mnemonic>vfnmsub231ps</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 be</opc>
            <opr>Vx Hx Wx</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsub132sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 9f</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmsub213sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 af</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmsub231sd</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=1 bf</opc>
            <opr>Vx Hx MqU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsub132ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9f</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmsub213ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 af</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfnmsub231ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 bf</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsub132ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 9b</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfmsub213ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 ab</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>vfmsub231ss</mnemonic>
		<cpuid>avx fma</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f38 /vexw=0 bb</opc>
            <opr>Vx Hx MdU</opr>
            <access source='scrape'>RW R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 69</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 69</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>

    </instruction>

    <instruction>
        <mnemonic>vfmaddps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 68</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 68</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6b</opc>
            <opr>Vx Hx MqU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6b</opc>
            <opr>Vx Hx Lx MqU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsubpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 5d</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 5d</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddsubps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 5c</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 5c</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubaddpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 5f</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 5f</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubaddps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 5e</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 5e</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6d</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6d</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6c</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6c</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>

    </instruction>

    <instruction>
        <mnemonic>vfmsubsd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6f</opc>
            <opr>Vx Hx MqU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6f</opc>
            <opr>Vx Hx Lx MqU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmsubss</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6e</opc>
            <opr>Vx Hx MdU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6e</opc>
            <opr>Vx Hx Lx MdU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfmaddss</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 6a</opc>
            <opr>Vx Hx MdU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 6a</opc>
            <opr>Vx Hx Lx MdU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsubsd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7f</opc>
            <opr>Vx Hx MqU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7f</opc>
            <opr>Vx Hx Lx MqU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsubss</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7e</opc>
            <opr>Vx Hx MdU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7e</opc>
            <opr>Vx Hx Lx MdU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmaddss</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7a</opc>
            <opr>Vx Hx MdU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7a</opc>
            <opr>Vx Hx Lx MdU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmaddsd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7b</opc>
            <opr>Vx Hx MqU Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7b</opc>
            <opr>Vx Hx Lx MqU</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmaddpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 79</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 79</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmaddps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 78</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 78</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsubps</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7c</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7c</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfnmsubpd</mnemonic>
		<cpuid>avx fma4</cpuid>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=0 7d</opc>
            <opr>Vx Hx Wx Lx</opr>
        </def>
		<def>
            <pfx>aso oso vexl rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexw=1 7d</opc>
            <opr>Vx Hx Lx Wx</opr>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntss</mnemonic>
		<vendor>amd</vendor>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 2b</opc>
            <opr>Md V</opr>
            <cpuid>sse4a</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>movntsd</mnemonic>
		<vendor>amd</vendor>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 2b</opc>
            <opr>Mq V</opr>
            <cpuid>sse4a</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>extrq</mnemonic>
		<vendor>amd</vendor>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 78</opc>
            <opr>W Ib Ib</opr>
            <cpuid>sse4a</cpuid>
        </def>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=66 0f 79</opc>
            <opr>V W</opr>
            <cpuid>sse4a</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>insertq</mnemonic>
		<vendor>amd</vendor>
        <def>
            <pfx>aso oso rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 78</opc>
            <opr>V W Ib Ib</opr>
            <cpuid>sse4a</cpuid>
        </def>
        <def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 79</opc>
            <opr>V W</opr>
            <cpuid>sse4a</cpuid>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndmk</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 1b</opc>
            <opr>B Mrdq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndcl</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>rexw rexr rexx rexb</pfx>
            <opc>/sse=f3 0f 1a</opc>
            <opr>B Erdq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndcu</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 1a</opc>
            <opr>B Erdq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndcn</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=f2 0f 1b</opc>
            <opr>B Erdq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndmov</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=66 0f 1a /m=32</opc>
            <opr>B BMqR</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=66 0f 1a /m=64</opc>
            <opr>B BMdqR</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=66 0f 1b /m=32</opc>
            <opr>BMqR B</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>rexr rexx rexb</pfx>
            <opc>/sse=66 0f 1b /m=64</opc>
            <opr>BMdqR B</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

	<!-- Note: for BNDLDX and BNDSTX we comment out the NOP definitions above -->
    <instruction>
        <mnemonic>bndldx</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>0f 1a</opc>
            <opr>B M</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>bndstx</mnemonic>
		<vendor>intel</vendor>
        <cpuid>mpx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>0f 1b</opc>
            <opr>M B</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>

    <!-- ****************** END CUSTOM RELYZE EXTENSTIONS -->

	<!-- http://support.amd.com/TechDocs/43479.pdf -->
    <instruction>
        <mnemonic>vfrczpd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso vexl rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 81</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfrczps</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso vexl rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 80</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfrczsd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 83</opc>
            <opr>Vx MqU</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vfrczss</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 82</opc>
            <opr>Vx MdU</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpcmov</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso vexl rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 a2</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
		<def>
            <pfx>oso aso vexl rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=1 a2</opc>
            <opr>Vx Hx Lx Wx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpcomb</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 cc</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomeqb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomneqb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueb</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 ce</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomled</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomged</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomeqd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomneqd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalsed</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrued</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 cf</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomeqq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomneqq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueq</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomub</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 ec</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltub</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleub</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtub</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeub</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomequb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomnequb</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseub</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueub</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomud</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 ee</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltud</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleud</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtud</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeud</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomequd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomnequd</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseud</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueud</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomuq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 ef</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltuq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleuq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtuq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeuq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomequq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomnequq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseuq</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueuq</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomuw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 ed</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltuw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomleuw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtuw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgeuw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomequw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomnequw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalseuw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtrueuw</mnemonic><def/></instruction>

	<instruction>
        <mnemonic>vpcomw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexl=0 /vexw=0 cd</opc>
            <opr>Vx Hx Wx Ib</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction><mnemonic>vpcomltw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomlew</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgtw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomgew</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomeqw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomneqw</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomfalsew</mnemonic><def/></instruction>
    <instruction><mnemonic>vpcomtruew</mnemonic><def/></instruction>

    <instruction>
        <mnemonic>vphaddbd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 C2</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddbq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 C3</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddbw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 C1</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphadddq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 cb</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddubd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 d2</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddubq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 d3</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddubw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 d1</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddudq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 db</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphadduwd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 d6</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphadduwq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 d7</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddwd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 c6</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphaddwq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 c7</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphsubbw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 e1</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphsubdq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 e3</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vphsubwd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 e2</opc>
            <opr>Vx Wx</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacsdd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 9e</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacsdqh</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 9f</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacsdql</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 97</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacssdd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 8e</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacssdqh</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 8f</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacssdql</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 87</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacsswd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 86</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacssww</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 85</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacswd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 96</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmacsww</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 95</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>vpmadcsswd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 a6</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpmadcswd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 b6</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpperm</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 a3</opc>
            <opr>Vx Hx Wx Lx</opr>
			<access source='manual'>W R R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=1 /vexl=0 a3</opc>
            <opr>Vx Hx Lx Wx</opr>
			<access source='manual'>W R R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vprotb</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 90</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 90</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def> <!-- fixed count version -->
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 c0</opc>
            <opr>Vx Wx Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vprotd</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 92</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 92</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def> <!-- fixed count version -->
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 c2</opc>
            <opr>Vx Wx Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vprotq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 93</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 93</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def> <!-- fixed count version -->
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 c3</opc>
            <opr>Vx Wx Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vprotw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 91</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 91</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def> <!-- fixed count version -->
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=08 /vexw=0 /vexl=0 c1</opc>
            <opr>Vx Wx Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshab</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 98</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 98</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshad</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 9a</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 9a</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshaq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 9b</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 9b</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshaw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 99</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 99</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshlb</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 94</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 94</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshld</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 96</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 96</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>vpshlq</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 97</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 97</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
		
    <instruction>
        <mnemonic>vpshlw</mnemonic>
		<vendor>amd</vendor>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 95</opc>
            <opr>Vx Wx Hx</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>oso aso rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 95</opc>
            <opr>Vx Hx Wx</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>	
	 
	<!-- AMD: TBM -->
	
	<!-- BEXTR - immediate form -->
    <instruction>
        <mnemonic>bextr</mnemonic>
		<eflags source='manual'>RUMUURRRRRR_</eflags>
		<vendor>amd</vendor>
		<cpuid>xop avx bmi1</cpuid>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0a /vexl=0 /vexw=0 10</opc>
            <opr>Gd Ed Id</opr>
			<access source='manual'>W R R</access>
        </def>
		<def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/vex=0a /vexl=0 /vexw=1 10</opc>
            <opr>Gq Eq Id</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blcfill</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=1</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=1</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blci</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 02 /reg=6</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 02 /reg=6</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blcic</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=5</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=5</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blcmsk</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 02 /reg=1</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 02 /reg=1</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>blcs</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=3</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=3</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>blsfill</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=2</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=2</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>blsic</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=6</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=6</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>t1mskc</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=7</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=7</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>tzmsk</mnemonic>
		<vendor>amd</vendor>
		<eflags source='manual'>RMMUUM______</eflags>
        <cpuid>xop avx</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=0 /vexl=0 01 /reg=4</opc>
            <opr>HRd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=09 /vexw=1 /vexl=0 01 /reg=4</opc>
            <opr>HRq Eq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
	<!-- AVX512 -->
	
    <instruction>
        <mnemonic>kaddw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 4a</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kaddb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 4a</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kaddq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 4a</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kaddd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 4a</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 41</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 41</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 41</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 41</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandnw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 42</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandnb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 42</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandnq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 42</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kandnd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 42</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kmovw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 90</opc>
            <opr>Kw KMw</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 91 /mod=!11</opc>
            <opr>KMw Kw</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 92 /mod=11</opc>
            <opr>Kw Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 93 /mod=11</opc>
            <opr>Gd KMw</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kmovb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 90</opc>
            <opr>Kb KMb</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 91 /mod=!11</opc>
            <opr>KMb Kb</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 92 /mod=11</opc>
            <opr>Kb Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 93 /mod=11</opc>
            <opr>Gd KMb</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kmovq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=1 90</opc>
            <opr>Kq KMq</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=1 91 /mod=!11</opc>
            <opr>KMq Kq</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f /vexl=0 /vexw=1 92 /mod=11</opc>
            <opr>Kq Eq</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f /vexl=0 /vexw=1 93 /mod=11</opc>
            <opr>Gq KMq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kmovd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=1 90</opc>
            <opr>Kd KMd</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=1 91 /mod=!11</opc>
            <opr>KMd Kd</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f /vexl=0 /vexw=0 92 /mod=11</opc>
            <opr>Kd Ed</opr>
			<access source='manual'>W R</access>
        </def>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=f2_0f /vexl=0 /vexw=0 93 /mod=11</opc>
            <opr>Gd KMd</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kunpckbw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 4b /mod=11</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kunpckwd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 4b /mod=11</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kunpckdq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 4b /mod=11</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>knotw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 44 /mod=11</opc>
            <opr>Kw KMw</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>knotb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 44 /mod=11</opc>
            <opr>Kb KMb</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>knotq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=1 44 /mod=11</opc>
            <opr>Kq KMq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>knotd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=1 44 /mod=11</opc>
            <opr>Kd KMd</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>

	<instruction>
        <mnemonic>korw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 45 /mod=11</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>korb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 45 /mod=11</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>korq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 45 /mod=11</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kord</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 45 /mod=11</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kortestw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 98 /mod=11</opc>
            <opr>Kw KMw</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kortestb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 98 /mod=11</opc>
            <opr>Kb KMb</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kortestq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=1 98 /mod=11</opc>
            <opr>Kq KMq</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kortestd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=1 98 /mod=11</opc>
            <opr>Kd KMd</opr>
			<access source='manual'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftlw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=1 32 /mod=11</opc>
            <opr>Kw KMw Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftlb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=0 32 /mod=11</opc>
            <opr>Kb KMb Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftlq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=1 33 /mod=11</opc>
            <opr>Kq KMq Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftld</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=0 33 /mod=11</opc>
            <opr>Kd KMd Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftrw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=1 30 /mod=11</opc>
            <opr>Kw KMw Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftrb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=0 30 /mod=11</opc>
            <opr>Kb KMb Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftrq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=1 31 /mod=11</opc>
            <opr>Kq KMq Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kshiftrd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f3a /vexl=0 /vexw=0 31 /mod=11</opc>
            <opr>Kd KMd Ib</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxnorw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 46 /mod=11</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxnorb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 46 /mod=11</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxnorq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 46 /mod=11</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxnord</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 46 /mod=11</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>ktestw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>RRMRRM______</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=0 99 /mod=11</opc>
            <opr>Kw KMw</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>ktestb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>RRMRRM______</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=0 99 /mod=11</opc>
            <opr>Kb KMb</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>ktestq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>RRMRRM______</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=0 /vexw=1 99 /mod=11</opc>
            <opr>Kq KMq</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>ktestd</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>RRMRRM______</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=0 /vexw=1 99 /mod=11</opc>
            <opr>Kd KMd</opr>
			<access source='manual'>R R</access>
        </def>
    </instruction>

    <instruction>
        <mnemonic>kxorw</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=0 47 /mod=11</opc>
            <opr>Kw KHw KMw</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxorb</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=0 47 /mod=11</opc>
            <opr>Kb KHb KMb</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxorq</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=0f /vexl=1 /vexw=1 47 /mod=11</opc>
            <opr>Kq KHq KMq</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>kxord</mnemonic>
		<vendor>intel</vendor>
		<eflags source='manual'>____________</eflags>
        <cpuid>avx avx512</cpuid>
		<def>
            <pfx>oso aso rexw rexr rexx rexb</pfx>
            <opc>/vex=66_0f /vexl=1 /vexw=1 47 /mod=11</opc>
            <opr>Kd KHd KMd</opr>
			<access source='manual'>W R R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>incsspd</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=5 /o=32</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>incsspq</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F AE /mod=11 /reg=5 /o=64</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>rdsspd</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F 1E /mod=11 /reg=1 /o=32</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>rdsspq</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
            <opc>/sse=F3 0F 1E /mod=11 /reg=1 /o=64</opc>
            <opr>Ev</opr>
            <access source='scrape'>R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>saveprevssp</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
			<opc>/sse=F3 0F 01 /mod=11 /reg=5 /rm=2</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>rstorssp</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
			<pfx>aso oso rexw rexr rexx rexb</pfx>
			<opc>/sse=F3 0F 01 /mod=!11 /reg=5</opc>
            <opr>M</opr>
            <access source='scrape'>W</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>wrssd</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>	
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 38 f6 /o=32</opc>
            <opr>Mv Gv</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>wrssq</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>	
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>0f 38 f6 /o=64</opc>
            <opr>Mv Gv</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>wrussd</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>	
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 f5 /o=32</opc>
            <opr>Mv Gv</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>	
	
    <instruction>
        <mnemonic>wrussq</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>	
            <pfx>aso oso rexr rexw rexx rexb</pfx>
            <opc>/sse=66 0f 38 f5 /o=64</opc>
            <opr>Mv Gv</opr>
            <access source='scrape'>W R</access>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>setssbsy</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
			<opc>/sse=f3 0f 01 /mod=11 /reg=5 /rm=0</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>clrssbsy</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
            <pfx>aso oso rexw rexr rexx rexb</pfx>
			<opc>/sse=f3 0f ae /mod=11 /reg=6 /m=64</opc>
            <opr>M</opr>
            <access source='scrape'>RW</access>	
        </def>
    </instruction>

    <instruction>
        <mnemonic>endbr64</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
			<opc>/sse=f3 0f 1e /mod=11 /reg=7 /rm=2</opc>
        </def>
    </instruction>
	
    <instruction>
        <mnemonic>endbr32</mnemonic>
		<vendor>intel</vendor>
		<cpuid>cet</cpuid>
        <def>
			<opc>/sse=f3 0f 1e /mod=11 /reg=7 /rm=3</opc>
        </def>
    </instruction>

</x86optable>
